Datasheet

Data Sheet ADAU1701
Rev. C | Page 25 of 52
I
2
C Read and Write Operations
Figure 22 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1701 issues an acknowledge by
pulling SDA low.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1701 knows to increment
its subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single-word read operation is shown in
Figure 24. Note that the first R/
W
bit is 0, indicating a write
operation. This is because the subaddress still needs to be
written to set up the internal address. After the
ADAU1701acknowledges the receipt of the subaddress, the
master must issue a repeated start command followed by the
chip address byte with the R/
W
set to 1 (read). This causes the
ADAU1701 SDA to reverse and begin driving data back to the
master. The master then responds every ninth pulse with an
acknowledge pulse to the ADAU1701.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1701 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other addresses
may have word lengths ranging from one to five bytes. The
ADAU1701 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 22 to Figure 25 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
S AS AS AS AS
SUBADDRESS
LOW
DATA BYTE 1 DATA BYTE 2 AS PDATA BYTE N
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
06412-022
Figure 22. Single Word I
2
C Write Format
S AS AS AS AS
SUBADDRESS
LOW
DATA-
WORD 1,
BYTE 1
DATA-
WORD 1,
BYTE 2
DATA-
WORD 2,
BYTE 1
DATA-
WORD 2,
BYTE 2
AS ASAS P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
06412-023
Figure 23. Burst Mode I
2
C Write Format
S AS AS AS S
SUBADDRESS
LOW
AM AMAS
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE N
P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
R/W = 1
06412-024
Figure 24. Single-Word I
2
C Read Format
S AS AS AS S
SUBADDRESS
LOW
AMAS
DATA-
WORD 1,
BYTE 1
AM
DATA-
WORD 1,
BYTE 2
P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
R/W = 1
0
6412-025
Figure 25. Burst Mode I
2
C Read Format