Datasheet

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Table Of Contents

FEATURES
APPLICATIONS
GENERAL DESCRIPTION
TABLE OF CONTENTS
REVISION HISTORY
FUNCTIONAL BLOCK DIAGRAM
SPECIFICATIONS
- ANALOG PERFORMANCE
- DIGITAL INPUT/OUTPUT
- POWER
- TEMPERATURE RANGE
- PLL AND OSCILLATOR
- REGULATOR
- DIGITAL TIMING SPECIFICATIONS
  - Digital Timing Diagrams
ABSOLUTE MAXIMUM RATINGS
- THERMAL RESISTANCE
- ESD CAUTION
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TYPICAL PERFORMANCE CHARACTERISTICS
SYSTEM BLOCK DIAGRAM
THEORY OF OPERATION
INITIALIZATION
- POWER-UP SEQUENCE
- CONTROL REGISTERS SETUP
  - DSP Core Control Register (Address 2076)
  - DAC Setup Register (Address 2087)
- RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE
- POWER REDUCTION MODES
- USING THE OSCILLATOR
- SETTING MASTER CLOCK/PLL MODE
- VOLTAGE REGULATOR
AUDIO ADCs
AUDIO DACs
CONTROL PORTS
- I2C PORT
  - Addressing
  - I2C Read and Write Operations
- SPI PORT
- SELF-BOOT
  - EEPROM Format
  - Writeback
SIGNAL PROCESSING
- NUMERIC FORMATS
  - Numerical Format: 5.23
- PROGRAMMING
RAMS AND REGISTERS
- ADDRESS MAPS
- PARAMETER RAM
  - Direct Read/Write
  - Safeload Write
- DATA RAM
- READ/WRITE DATA FORMATS
CONTROL REGISTER MAP
CONTROL REGISTER DETAILS
- 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS
- 2056 (0x0808)—GPIO PIN SETTING REGISTER
- 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS
- 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS
- 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
- 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS
- 2076 (0x081C)—DSP CORE CONTROL REGISTER
- 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
- 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
- 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS
- 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL
- 2084 (0x0824)—AUXILIARY ADC ENABLE
- 2086 (0x0826)—OSCILLATOR POWER-DOWN
- 2087 (0x0827)—DAC SETUP
MULTIPURPOSE PINS
- AUXILIARY ADC
- GENERAL-PURPOSE INPUT/OUTPUT PINS
- SERIAL DATA INPUT/OUTPUT PORTS
LAYOUT RECOMMENDATIONS
- PARTS PLACEMENT
- GROUNDING
TYPICAL APPLICATION SCHEMATICS
- SELF-BOOT MODE
- I2C CONTROL
- SPI CONTROL
OUTLINE DIMENSIONS
- ORDERING GUIDE

ADAU1701 Data Sheet

Rev. C | Page 24 of 52

R/W

0

SCL

SDA

SDA

(CONTINUED)

SCL

(CONTINUED)

11 0

ADDR

SEL

10

START BY

MASTER

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

SUBADDRESS BYTE 1

FRAME 3

SUBADDRESS BYTE 2

FRAME 4

DATA BYTE 1

ACK BY

ADAU1701

ACK BY

ADAU1701

ACK BY

ADAU1701

ACK BY

ADAU1701

STOP BY

MASTER

06412-020

Figure 20. I

2

C Write to ADAU1701 Clocking

R/W

SCL

SDA 0 0 011 1

SDA

(CONTINUED)

SCL

(CONTINUED)

SDA

(CONTINUED)

SCL

(CONTINUED)

ADR

SEL

START BY

MASTER

FRAME 2

SUBADDRESS BYTE 1

FRAME 3

SUBADDRESS BYTE 2

FRAME 4

CHIP ADDRESS BYTE

FRAME 1

CHIP ADDRESS BYTE

FRAME 6

READ DATA BYTE 2

FRAME 5

READ DATA BYTE 1

ACK BY

ADAU1701

ACK BY

ADAU1701

ACK BY

ADAU1701

ACK BY

ADAU1701

STOP BY

MASTER

ACK BY

MASTER

ACK BY

MASTER

REPEATED

START BY MASTER

R/W

ADDR

SEL

06412-021

Figure 21. I

2

C Read from ADAU1701 Clocking