Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- TABLE OF CONTENTS
- REVISION HISTORY
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- SYSTEM BLOCK DIAGRAM
- THEORY OF OPERATION
- INITIALIZATION
- AUDIO ADCs
- AUDIO DACs
- CONTROL PORTS
- SIGNAL PROCESSING
- RAMS AND REGISTERS
- CONTROL REGISTER MAP
- CONTROL REGISTER DETAILS
- 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS
- 2056 (0x0808)—GPIO PIN SETTING REGISTER
- 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS
- 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS
- 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
- 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS
- 2076 (0x081C)—DSP CORE CONTROL REGISTER
- 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
- 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
- 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS
- 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL
- 2084 (0x0824)—AUXILIARY ADC ENABLE
- 2086 (0x0826)—OSCILLATOR POWER-DOWN
- 2087 (0x0827)—DAC SETUP
- MULTIPURPOSE PINS
- LAYOUT RECOMMENDATIONS
- TYPICAL APPLICATION SCHEMATICS
- OUTLINE DIMENSIONS
Data Sheet ADAU1701
Rev. C | Page 15 of 52
SYSTEM BLOCK DIAGRAM
22pF
22pF
ADAU1701
ADCs DACs
VOUT0
VOUT1
VOUT2
VOUT3
ADC0
IOVDD PVDD
AVDD DVDD
VDRIVE
ADC1
ADC_RES
FILTA
FILTD
CM
ADDR0
ADDR1/CDATA/WB
CLATCH/WP
SDA/COUT
SCL/CCLK
SELFBOOT
RESET
RSVD
EEPROM,
MICROCONTROLLER,
AND/OR SELFBOOT
LOGIC
AGND DGND PGND
OSCO
MCLKI
PLL_MODE1
PLL_MODE0
PLL_LF
MP11
MP10
MP9
MP8
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
RESET LOGIC
100nF10µF
100nF10µF
+
+
DAC OUTPUT FILTERS
(ACTIVE OR PASSIVE)
MULTIPURPOSE
PIN INTERFACES
100nF
10µF
18kΩ
18kΩ
18kΩ
AUDIO ADC
INPUT SIGNALS
PLL
SETTINGS
3.3V
3MHz TO 25MHz
56nF3.3nF
475Ω
100Ω
3.3V TO 1.8V
REGULATOR
CIRCUIT
3.3V
100nF
100nF
100nF
+
100nF
10µF
+
10µF
+
06412-012
Figure 12. System Block Diagram