Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- TABLE OF CONTENTS
- REVISION HISTORY
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- SYSTEM BLOCK DIAGRAM
- THEORY OF OPERATION
- INITIALIZATION
- AUDIO ADCs
- AUDIO DACs
- CONTROL PORTS
- SIGNAL PROCESSING
- RAMS AND REGISTERS
- CONTROL REGISTER MAP
- CONTROL REGISTER DETAILS
- 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS
- 2056 (0x0808)—GPIO PIN SETTING REGISTER
- 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS
- 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS
- 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS
- 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS
- 2076 (0x081C)—DSP CORE CONTROL REGISTER
- 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
- 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
- 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS
- 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL
- 2084 (0x0824)—AUXILIARY ADC ENABLE
- 2086 (0x0826)—OSCILLATOR POWER-DOWN
- 2087 (0x0827)—DAC SETUP
- MULTIPURPOSE PINS
- LAYOUT RECOMMENDATIONS
- TYPICAL APPLICATION SCHEMATICS
- OUTLINE DIMENSIONS
Data Sheet ADAU1701
Rev. C | Page 13 of 52
Pin No. Mnemonic Type
1
Description
33 PGND PWR PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple PGND to PVDD by using a 100 nF capacitor.
34 PVDD PWR 3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. Decouple this pin to
PGND by using a 100 nF capacitor.
35
PLL_LF
A_OUT
PLL Loop Filter Connection. Two capacitors and a resistor need to be connected to this pin, as
shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details.
36, 48 AVDD PWR 3.3 V Analog Supply. Decouple this pin to AGND by using a 100 nF capacitor.
38, 39 PLL_MODE0,
PLL_MODE1
D_IN PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency of the master
clock PLL. See the Setting Master Clock/PLL Mode section for more details.
40 CM A_OUT 1.5 V Common-Mode Reference. Connect a 47 μF decoupling capacitor between this pin and
ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is not
critical. This pin can be used to bias external analog circuits, as long as those circuits are not
drawing current from the pin (such as when CM is connected to the noninverting input of
an op amp).
41 FILTD A_OUT DAC Filter Decoupling Pin. Connect a 10 μF capacitor between this pin and ground. The
capacitor material is not critical. The voltage on this pin is 1.5 V.
43 to 46 VOUT3 A_OUT VOUT DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
44 VOUT2 A_OUT VOUT2 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
45 VOUT1 A_OUT VOUT1 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
46 VOUT0 A_OUT VOUT0 DAC Output. The full-scale output voltage is 0.9 V rms. This output can be used with
either an active or passive output reconstruction filter. See the Audio DACs section for details.
47 FILTA A_OUT ADC Filter Decoupling Pin. A 10 μF capacitor should be connected between this pin and
ground. The capacitor material is not critical. The voltage on this pin is 1.5 V.
1
PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog
input/output.