Datasheet

Data Sheet ADAU1701
Rev. C | Page 11 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
AVDD
PLL_LF
PVDD
PGND
MCLKI
OSCO
RSVD
MP2
MP3
MP8
MP9
DGND
DVDD
MP7 MP6
MP10
VDRIVE
IOVDD
MP11
ADDR1/CDATA/WB
CLATCH/WP
SDA/COUT
SCL/CCLK
DVDD
AGND
ADC0
ADC_RES
ADC1
RESET
SELFBOOT
ADDR0
MP4
MP5
MP1
MP0
DGND
13 14 15 16 17 18 19 20 21 22
23
24
48 47 46 45 44 43 42 41 40 39 38 37
AVDD FILTA VOUT0
VOUT1
VOUT2 VOUT3
AGND FILTD
CM
PLL_MODE1 PLL_MODE0
AGND
ADAU1701
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
06412-007
Figure 7. 48-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1, 37, 42 AGND PWR Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple AGND to an AVDD pin with a 100 nF capacitor.
2
ADC0
A_IN
Analog Audio Input 0. Full-scale 100 μA rms input. Current input allows input voltage level
to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input. See
the
Audio ADCs section for details.
3 ADC_RES A_IN ADC Reference Current. Set the full-scale current of the ADCs with an external 18 kΩ resistor
connected between this pin and ground. See the Audio ADCs section for details.
4 ADC1 A_IN Analog Audio Input 1. Full-scale 100 μA rms input. Current input allows the input voltage
level to be scaled with an external resistor. An 18 kΩ resistor gives a 2 V rms full-scale input.
5
RESET
D_IN Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1701 exits
reset on a low-to-high edge. For more information about initialization, see the Power-Up
Sequence section for details.
6 SELFBOOT D_IN Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting
this pin high initiates a self-boot operation when the ADAU1701 is brought out of a reset. This
pin can be tied directly to the control voltage or pulled up/down with a resistor. See the
Self-Boot section for details.
7 ADDR0 D_IN I
2
C and SPI Address 0. In combination with ADDR1 function on Pin 20, this pin allows up to
four ADAU1701 devices to be used on the same I
2
C bus and up to two ICs to be used with a
common SPI CLATCH signal. See the I
2
C Port section for details.
8
MP4
D_IO
Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK). See the Multipurpose Pins
section for more details.
9 MP5 D_IO Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK). See the Multipurpose Pins
section for more details.
10 MP1 D_IO Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0). See the Multipurpose Pins
section for more details.
11 MP0 D_IO Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1). See the Multipurpose Pins
section for more details.
12, 25 DGND PWR Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. Decouple DGND to a DVDD pin with a 100 nF capacitor.
13, 24 DVDD PWR 1.8 V Digital Supply. This can be supplied either externally or generated from a 3.3 V supply
with the on-board 1.8 V regulator. Decouple DVDD to DGND with a 100 nF capacitor.