Datasheet

ADAU1381
Rev. B | Page 82 of 84
Register 16627 (0x40F3), Serial Output Route Control
Bits[3:0], Output Routing
These bits select where the ADC outputs are routed in the serial data stream (see Figure 72).
Table 73. Serial Output Route Control Register
Bits Description Default
[7:4] Reserved
[3:0] Output routing 0000
0000: ADCs to sound engine to serial outputs
0001: ADCs [L, R] to serial output [L0, R0]
1
0010: reserved
0011: ADCs [L, R] to serial output [L1, R1]
1
0100: reserved
0101: ADCs [L, R] to serial output [L2, R2]
1
0110: reserved
0111: ADCs [L, R] to serial output [L3, R3]
1
1000: reserved
1001: ADCs [L, R] to serial output [R0, L0]
1
1010: reserved
1011: ADCs [L, R] to serial output [R1, L1]
1
1100: reserved
1101: ADCs [L, R] to serial output [R2, L2]
1
1110: reserved
1111: ADCs [L, R] to serial output [R3, L3]
1
1
Lx = left side of Channel x; Rx = right side of Channel x.
1/f
LRCLK
LRCLK
STEREO CHANNELS
L0
R0
TDM 4 CHANNELS
L0
R0
L1
R1
TDM 8 CHANNELS
L0
R0 L1 R1 L2 R2 L3 R3
08313-070
Figure 72. Serial Port Routing Control