Datasheet

ADAU1381
Rev. B | Page 77 of 84
DIGITAL SUBSYSTEM CONFIGURATION
Register 16512 (0x4080), Digital Power-Down 0
Bit 7, ADC Engine
Setting this bit to 0 disables the ADCs and the digital micro-
phone inputs.
Bit 6, Memory Controller
Setting this bit to 0 disables all memory access, which disables
the sound engine, ADCs, and DACs, as well as prohibits memory
access via the control port.
Bit 5, Clock Domain Transfer
Setting this bit to 0—in conjunction with Bit 4, serial ports—
disables the serial ports.
Bit 4, Serial Ports
Setting this bit to 0—in conjunction with Bit 5, clock domain
transfer—disables the serial ports.
Bit 3, Serial Output Routing
Setting this bit to 0 disables the routing paths for the record signal
path, which goes from the sound engine to the serial port output.
Bit 2, Serial Input Routing
Setting this bit to 0 disables the routing paths for the play-
back signal path, which goes from the serial input ports to the
sound engine.
Bit 1, Serial Port, ADC, DAC, and Frame Pulse Clock
Generator
Setting this bit to 0 disables the internal clock generator, which
generates all master clocks for the serial ports, sound engine,
ADCs, and DACs. This bit must be enabled if audio is being
passed through the ADAU1381.
Bit 0, Sound Engine
Setting this bit to 0 disables the sound engine and makes the
memory inaccessible. This bit must be enabled in order to
process audio and change parameter values.
Table 65. Digital Power-Down 0 Register
Bit Description Default
7 ADC engine 0
0: disabled
1: enabled
6 Memory controller 0
0: disabled
1: enabled
5 Clock domain transfer (when using the serial ports) 0
0: disabled
1: enabled
4 Serial ports 0
0: disabled
1: enabled
3 Serial output routing 0
0: disabled
1: enabled
2 Serial input routing 0
0: disabled
1: enabled
1 Serial port, ADC, DAC, and frame pulse clock generator 0
0: disabled
1: enabled
0 Sound engine 0
0: disabled
1: enabled