Datasheet

ADAU1381
Rev. B | Page 72 of 84
Register 16430 (0x402E), Serial Port Pad Control 1
Bit 3, ADC_SDATA Pin Drive Strength
This bit sets the drive strength of the ADC_SDATA pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
Bit 2, DAC_SDATA Pin Drive Strength
This bit sets the drive strength of the DAC_SDATA pin. Low mode
yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =
1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA
when IOVDD = 1.8 V.
Bit 1, LRCLK Pin Drive Strength
This bit sets the drive strength of the LRCLK pin. Low mode yields
2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when
IOVDD = 1.8 V.
Bit 0, BCLK Pin Drive Strength
This bit sets the drive strength of the BCLK pin. Low mode yields
2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.
High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when
IOVDD = 1.8 V.
Table 60. Serial Port Pad Control 1 Register
Bits Description Default
[7:4] Reserved
3 ADC_SDATA pin drive strength 0
0: low
1: high
2 DAC_SDATA pin drive strength 0
0: low
1: high
1 LRCLK pin drive strength 0
0: low
1: high
0 BCLK pin drive strength 0
0: low
1: high