Datasheet

ADAU1381

Rev. B | Page 70 of 84

PAD CONFIGURATION

Figure 71 shows a block diagram of the pad design for the GPIO/serial port and communications port pins.

PAD

OUTPUT PULL-UP ENABLE

(CONTROLS PMOS)

DATA OUT

DIGITAL

SUPPLY

I/O

SUPPLY

DEBOUNCE

LEVEL

SHIFTER

PULL-UP

ENABLE

PULL-DOWN

ENABLE

LEVEL

SHIFTER

INPUT

ESD

LEVEL

SHIFTER

WEAK PULL-UP/PULL-DOWN

240kΩ NOMINAL

190kΩ WORST CASE

INPUT

ENABLE

DEBOUNCE

ENABLE

6×

12×

OUTPUT ENABLE

DATA IN

OUTPUT

CONTROL

LOGIC

WEAK PULL-UP ENABLE

WEAK PULL-DOWN ENABLE

DRIVE STRENGTH

(CONTROLS NUMBER OF PARALLEL TRANSISTOR PAIRS)

IOVDD = 3.3V; LOW = 2.0mA, HIGH = 4.0mA

IOVDD = 1.8V; LOW = 0.75mA, HIGH = 1.5mA

08313-069

Figure 71. Pad Configuration, Internal Design