Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADAU1381BCBZ-RL7

ADAU1381

Rev. B | Page 63 of 84

PLAYBACK PATH CONFIGURATION

Bit 5, Left DAC Mute

This bit mutes the left DAC output. It does not have any slew

and is updated immediately when the register write has been

completed. This results in an abrupt cutoff of the audio output

and should therefore be preceded by a soft mute in the sound

engine or a slew mute using the DAC attenuator.

Bits[4:1], Left Playback Beep Gain

These bits set the gain of the beep signal in the left playback

path. If the zero-crossing detector is activated, the change in

gain is applied on the next detected zero crossing or when the

timeout period expires, whichever comes first. The gain control

is in 3 dB increments and should not be incremented more than

3 dB at a time in order to avoid audible artifacts on the output.

Bit 6, Right DAC Mute

This bit mutes the right DAC output. It does not have any slew

and is updated immediately when the register write has been

completed. This results in an abrupt cutoff of the audio output

and should therefore be preceded by a soft mute in the sound

engine or a slew mute using the DAC attenuator.

Bits[4:1], Right Playback Beep Gain

These bits set the gain of the beep signal in the right playback

path. If the zero-crossing detector is activated, the change in

gain is applied on the next detected zero crossing or when the

timeout period expires, whichever comes first. The gain control

is in 3 dB increments and should not be incremented more than

3 dB at a time in order to avoid audible artifacts on the output.

Table 47. Playback Mixer Left Control Register

Bits Description Default

[7:6] Reserved

5 Left DAC mute 0

0: muted

1: unmuted

[4:1] Left playback beep gain 0000

0000: muted

0001: −15 dB

0010: −12 dB

0011: −9 dB

0100: −6 dB

0101: −3 dB

0110: 0 dB

0111: +3 dB

1000: +6 dB

0 Reserved

Table 48. Playback Mixer Right Control Register

Bits Description Default

7 Reserved

6 Right DAC mute 0