Datasheet

ADAU1381
Rev. B | Page 47 of 84
Table 33. Fractional PLL Parameter Settings for f
S
= 44.1 kHz (f
S
= 44.1 kHz, Core Clock = 256 × 44.1 kHz, PLL Clock = 45.1584 MHz)
MCLK Input (MHz) Input Divider (X) Integer (R) Denominator (M) Numerator (N)
12 1 3 625 477
13 1 3 8125 3849
14.4 1 3 125 17
19.2 1 2 125 44
19.68 1 2 2035 302
19.8 1 2 1375 386
Table 34. Fractional PLL Parameter Settings for f
S
= 48 kHz (f
S
= 48 kHz, Core Clock = 256 × 48 kHz, PLL Clock = 49.152 MHz)
MCLK Input (MHz) Input Divider (X) Integer (R) Denominator (M) Numerator (N)
12 1 4 125 12
13 1 3 1625 1269
14.4 1 3 75 31
19.2 1 2 25 14
19.68 1 2 205 102
19.8 1 2 825 398