Datasheet

ADAU1381
Rev. B | Page 44 of 84
CLOCK MANAGEMENT, INTERNAL REGULATOR,
AND PLL CONTROL
Register 16384 (0x4000), Clock Control
The clock control register sets the clocking scheme for the
ADAU1381. The system clock can be generated from either the
PLL or directly from the MCKI (master clock input) pin. Addi-
tionally, the MCKO (master clock output) pin can be configured.
Bits[6:5], MCKO Frequency
These bits set the frequency to be output on MCKO as a multiple
of the base sampling frequency (32×, 64×, 128×, or 256×). The
MCKO pin can be used to provide digital microphones with a clock.
Bit 4, MCKO Enable
This bit enables or disables the MCKO pin.
Bit 3, Clock Source Select
The clock source select bit either routes the MCLK input through
the PLL or bypasses the PLL. When using the PLL, the output of
the PLL is always 1024 × f
S
, and Bits[2:1] should be set to 11.
PLL parameters can be set in the PLL control register. Inputs
directly from MCKI require an exact clock rate as described in
the Bits[2:1], Input Master Clock Frequency section.
Bits[2:1], Input Master Clock Frequency
The maximum clock speed allowed is 1024 × 48 kHz. These bits set
the expected input master clock frequency for proper clock divider
values in order to output a constant system clock of 256 × f
S
. When
using the PLL, these bits must always be set to 1024 × f
S
. When
bypassing the PLL, the external clock frequency on the MCKI pin
must be 256 × f
S
, 512 × f
S
, 768 × f
S
, or 1024 × f
S
. Table 29 and
Table 30 show the relationship between the system clock and the
internal master clock for base sampling frequencies of 44.1 kHz
and 48 kHz.
Bit 0, Core Clock Enable
This bit enables the internal master clock to start the IC.
Table 28. Clock Control Register
Bits Description Default
7 Reserved
[6:5] MCKO frequency 00
00: 32 × f
S
01: 64 × f
S
10: 128 × f
S
11: 256 × f
S
4 MCKO enable 0
0: disabled
1: enabled
3 Clock source select 0
0: direct from MCKI pin
1: PLL clock
[2:1] Input master clock frequency 00
00: 256 × f
S
01: 512 × f
S
10: 768 × f
S
11: 1024 × f
S
0 Core clock enable 0
0: core clock disabled
1: core clock enabled
Table 29. Core Clock Output for f
S
= 44.1 kHz
MCLK Input Setting MCLK Input Value MCLK Input Divider Core Clock
256 × f
S
11.2896 MHz 1 11.2896 MHz
512 × f
S
22.5792 MHz 2 11.2896 MHz
768 × f
S
33.8688 MHz 3 11.2896 MHz
1024 × f
S
45.1584 MHz 4 11.2896 MHz
Table 30. Core Clock Output for f
S
= 48 kHz
MCLK Input Setting MCLK Input Value MCLK Input Divider Core Clock
256 × f
S
12.288 MHz 1 12.288 MHz
512 × f
S
24.576 MHz 2 12.288 MHz
768 × f
S
36.864 MHz 3 12.288 MHz
1024 × f
S
49.152 MHz 4 12.288 MHz