Datasheet

ADAU1381
Rev. B | Page 39 of 84
LRCL
K
BCLK
SDATA MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1/ f
S
08313-045
Figure 47. I
2
S Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB LSB MSB
RIGHT CHANNEL
LSB
1/ f
S
08313-046
Figure 48. Left-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB LSB MSB
RIGHT CHANNEL
LSB
1/ f
S
08313-047
Figure 49. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
DATA
SLOT 1 SLOT 4 SLOT 5
32 BCLKs
MSB MSB – 1 MSB – 2
256 BCLKs
SLOT 2 SLOT 3 SLOT 6 SLOT 7 SLOT 8
LRCLK
BCLK
DATA
08313-048
Figure 50. TDM Mode
LRCL
K
SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7
CH
0
BCLK
SDATA
MSB TDM
8TH
CH
32
BCLKs
MSB TDM
08313-049
Figure 51. TDM Mode with Pulse Word Clock