Datasheet

ADAU1381
Rev. B | Page 33 of 84
CONTROL PORTS
The ADAU1381 can operate in one of two control modes: I
2
C
control or SPI control.
The ADAU1381 has both a 4-wire SPI control port and a 2-wire
I
2
C bus control port. Each can be used to set the registers. The
part defaults to I
2
C mode but can be put into SPI control mode
by pulling the
CLATCH
pin low three times.
The control port is capable of full read/write operation for all
addressable registers. Most sound engine processing parameters
are controlled by writing new values to the sound engine parameter
register using the control port. Other functions, such as mute,
input/output mode control, and analog signal paths, can be
programmed by writing to the appropriate registers.
All addresses can be accessed in either a single-address mode or
a burst mode. The first byte (Byte 0) of a control port write contains
the 7-bit chip address plus the R/
W
bit. The next two bytes (Byte 1
and Byte 2) together form the subaddress of the register location
within the ADAU1381. All subsequent bytes (starting with Byte 3)
contain the data, such as control port data, register data, or sound
engine parameter data. The number of bytes per word depends
on the type of data that is being written. The exact formats for
specific types of writes and reads are shown in to
.
Figure 40
Figure 43
The ADAU1381 has several mechanisms for updating sound
engine parameters in real time without causing pops or clicks.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 2 0 details these
multiple functions.
Table 20. Control Port Pin Functions
Pin I
2
C Mode SPI Mode
SCL/CCLK SCL—input CCLK—input
SDA/COUT SDA—open-collector output COUT—output
ADDR1/CLATCH
I
2
C Address Bit 1—input
CLATCH
—input
ADDR0/CDATA I
2
C Address Bit 0—input CDATA—input
I
2
C PORT
The ADAU1381 supports a 2-wire serial (I
2
C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1381 and the system I
2
C master controller.
In I
2
C mode, the ADAU1381 is always a slave on the bus, meaning
it cannot initiate a data transfer. Each slave device is recognized by
a unique address. The address byte format is shown in Tabl e 21.
The address resides in the first seven bits of the I
2
C write. The
LSB of this byte sets either a read or write operation. Logic 1
corresponds to a read operation, and Logic 0 corresponds to a
write operation. The full byte addresses, including the pin settings
and R/
W
bit, are shown in . Table 2 2
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single-word write unless a
stop condition is encountered. The registers in the ADAU1381
range in width from one to six bytes; therefore, the auto-increment
feature knows the mapping between subaddresses and the word
length of the destination register. A data transfer is always
terminated by a stop condition.
Both SDA and SCL should have 2.0 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines should
not be more than AVDD1.
Table 21. I
2
C Address Byte Format
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
0 1 1 1 0 ADDR1 ADDR0
R/W
Table 22. I
2
C Addresses
ADDR1 ADDR0
R/
W
Slave Address
0 0 0 0x70
0 0 1 0x71
0 1 0 0x72
0 1 1 0x73
1 0 0 0x74
1 0 1 0x75
1 1 0 0x76
1 1 1 0x77
Addressing
Initially, each device on the I
2
C bus is in an idle state and
monitoring the SDA and SCL lines for a start condition and
the proper address. The I
2
C master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address or
an address and data stream follow. All devices on the bus respond
to the start condition and shift the next eight bits (the 7-bit
address plus the R/
W
bit), MSB first. The device that recognizes
the transmitted address responds by pulling the data line low
during the ninth clock pulse. This ninth bit is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and return to the idle condition.
The R/
W
bit determines the direction of the data. A Logic 0 on the
LSB of the first byte means the master writes information to the
peripheral, whereas a Logic 1 means the master reads information
from the peripheral after writing the subaddress and repeating
the start address. A data transfer takes place until a stop condition
is encountered. A stop condition occurs when SDA transitions
from low to high while SCL is held high. shows the
timing of an I
2
C write, and shows an I
2
C read.
Figure 38
Figure 39