Datasheet

ADAU1381
Rev. B | Page 29 of 84
The ADC and DAC sampling rate can be set in Register 16407
(0x4017), Converter Control 0, Bits[2:0], converter sampling
rate. The sound engine sampling rate and serial port sampling
rate are similarly set in Register 16619 (0x40EB), sound engine
frame rate, Bits[3:0], sound engine frame rate, and Register
16632 (0x40F8), serial port sampling rate, Bits[2:0], serial port
control sampling rate, respectively.
Table 18 and Table 19 depict example sampling rate settings.
The (1 × 256) case is the base sampling rate.
Table 18. Sampling Rates for 256 × 48 kHz Core Clock
Core Clock Sampling Rate Divider Sampling Rate
12.288 MHz (1 × 256) 48 kHz
(6 × 256) 8 kHz
(4 × 256) 12 kHz
(3 × 256) 16 kHz
(2 × 256) 24 kHz
(1.5 × 256) 32 kHz
(0.5 × 256) 96 kHz
Table 19. Sampling Rates for 256 × 44.1 kHz Core Clock
Core Clock Sampling Rate Divider Sampling Rate
11.2896 MHz (1 × 256) 44.1 kHz
(6 × 256) 7.35 kHz
(4 × 256) 11.025 kHz
(3 × 256) 14.7 kHz
(2 × 256) 22.05 kHz
(1.5 × 256) 29.4 kHz
(0.5 × 256) 88.2 kHz