Datasheet

ADAU1361
Rev. C | Page 46 of 80
CONTROL REGISTER DETAILS
All registers except for the PLL control register are 1-byte write and read registers.
R0: Clock Control, 16,384 (0x4000)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved CLKSRC INFREQ[1:0] COREN
Table 27. Clock Control Register
Bits Bit Name Description
3 CLKSRC
Clock source select.
0 = direct from MCLK pin (default).
1 = PLL clock.
[2:1] INFREQ[1:0]
Input clock frequency. Sets the core clock rate that generates the core clock. If the PLL is used, this value is
automatically set to 1024 × f
S
.
Setting Input Clock Frequency
00 256 × f
S
(default)
01 512 × f
S
10 768 × f
S
11 1024 × f
S
0 COREN
Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled).
0 = core clock disabled (default).
1 = core clock enabled.
R1: PLL Control, 16,386 (0x4002)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 M[15:8]
1 M[7:0]
2 N[15:8]
3 N[7:0]
4 Reserved R[3:0] X[1:0] Type
5 Reserved Lock PLLEN
Table 28. PLL Control Register
Byte Bits Bit Name Description
0 [7:0] M[15:8] PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number.
1 [7:0] M[7:0] PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.
M[15:8] (MSB) M[7:0] (LSB) Value of M
00000000 00000000 0
… … …
00000000 11111101 253 (default)
… … …
11111111 11111111 65,535
2 [7:0] N[15:8] PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.
3 [7:0] N[7:0] PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.
N[15:8] (MSB) N[7:0] (LSB) Value of N
00000000 00000000 0
… … …
00000000 00001100 12 (default)
… … …
11111111 11111111 65,535