Datasheet

ADAU1361
Rev. C | Page 43 of 80
LRCL
K
BCLK
SDATA MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1/f
S
07679-040
Figure 57. I
2
S Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB LSB MSB
RIGHT CHANNEL
LSB
07679-041
1/ f
S
Figure 58. Left-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB LSB MSB
RIGHT CHANNEL
LSB
07679-042
1/ f
S
Figure 59. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
S
DAT
A
SLOT 0 SLOT 2
32 BCLKs
MSB MSB – 1 MSB – 2
128 BCLKs
SLOT 1 SLOT 3
LRCLK
BCLK
SDATA
07679-043
Figure 60. TDM 4 Mode
LRCLK
SLOT 0 SLOT 1 SLOT 2 SLOT 3
CH
0
BCLK
SDATA
32 BCLKs
07679-044
MSB TDM
Figure 61. TDM 4 Mode with Pulse Word Clock