Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL ADAU1361 FEATURES GENERAL DESCRIPTION 24-bit stereo audio ADC and DAC: >98 dB SNR Sampling rates from 8 kHz to 96 kHz Low power: 7 mW record, 7 mW playback, 48 kHz at 1.
ADAU1361 TABLE OF CONTENTS Features .............................................................................................. 1 Core Clock................................................................................... 26 Applications....................................................................................... 1 Sampling Rates............................................................................ 26 General Description ..............................................................
ADAU1361 REVISION HISTORY 9/10—Rev. B to Rev. C Changes to Figure 1...........................................................................1 5/10—Rev. A to Rev. B Changes to Burst Mode Writing and Reading Section ..............38 Changes to Table 26 ........................................................................45 Change to Table 43..........................................................................58 Added R67: Dejitter Control, 16,438 (0x4036) Section .............73 12/09—Rev. 0 to Rev.
ADAU1361 SPECIFICATIONS Supply voltage (AVDD) = 3.3 V, TA = 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V, unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
ADAU1361 Parameter PSEUDO-DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Volume Control Step Volume Control Range PGA Boost Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Common-Mode Rejection Ratio FULL DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (
ADAU1361 Parameter Interchannel Isolation Common-Mode Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.
ADAU1361 Parameter DAC TO HEADPHONE/EARPIECE OUTPUT Full-Scale Output Voltage (0 dB) Total Harmonic Distortion + Noise 16 Ω load 32 Ω load Power Supply Rejection Ratio Interchannel Isolation REFERENCE Common-Mode Reference Output Test Conditions/Comments PO = output power per channel Min Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V −4 dBFS AVDD = 1.8 V, PO = 6.4 mW AVDD = 3.3 V, PO = 21.1 mW AVDD = 1.8 V, PO = 3.8 mW AVDD = 3.3 V, PO = 10.
ADAU1361 TYPICAL CURRENT CONSUMPTION Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ −1 dBFS, DAC input @ 0 dBFS. For total power consumption, add the IOVDD current listed in Table 2. Table 3. Operating Voltage AVDD = IOVDD = 3.
ADAU1361 TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, integer PLL, input sample rate = 48 kHz, input tone = 1 kHz. Pseudo-differential input to ADCs, DACs to line output with 10 kΩ load. ADC input @ −1 dBFS, DAC input @ 0 dBFS. In Table 4, the mixer boost and power management conditions are set for MXBIAS[1:0], ADCBIAS[1:0], HPBIAS[1:0], and DACBIAS[1:0].
ADAU1361 DIGITAL FILTERS Table 5. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode All modes, typ @ 48 kHz Factor Min 0.4375 fS Max Unit 22.9844/fS 21 ±0.015 24 27 67 479 kHz dB kHz kHz dB μs 0.4535 fS 0.3646 fS 22 35 kHz kHz dB dB kHz kHz kHz kHz dB dB μs μs 0.5 fS 0.
ADAU1361 DIGITAL TIMING SPECIFICATIONS −40°C < TA < +85°C, IOVDD = 3.3 V ± 10%. Table 7. Digital Timing Parameter MASTER CLOCK tMP tMP tMP tMP SERIAL PORT tBIL tBIH tLIS tLIH tSIS tSIH tSODM SPI PORT fCCLK tCCPL tCCPH tCLS tCLH tCLPH tCDS tCDH tCOD I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tSCR tSCF tSDR tSDF tBFT DIGITAL MICROPHONE tDCF tDCR tDDV tDDH tMIN 74 37 24.7 18.5 Limit tMAX Unit Description 488 244 162.7 122 ns ns ns ns MCLK period, 256 × fS mode. MCLK period, 512 × fS mode.
ADAU1361 DIGITAL TIMING DIAGRAMS tLIH tBIH BCLK tBIL tLIS LRCLK tSIS DAC_SDATA LEFT-JUSTIFIED MODE MSB MSB – 1 tSIH tSIS DAC_SDATA I2S MODE MSB tSIH tSIS tSIS DAC_SDATA RIGHT-JUSTIFIED MODE LSB MSB tSIH tSIH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 07679-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2.
ADAU1361 tCLS tCLH tCLPH tCCPL tCCPH CLATCH CCLK CDATA tCDH tCDS COUT 07679-004 tCOD Figure 4. SPI Port Timing tDS tSCH tSCH SDA tSCLH SCL tSCLL tSCS tSCF tBFT Figure 5. I2C Port Timing tDCF tDCR CLK DATA1/ DATA2 DATA1 DATA2 tDDH tDDV tDDV DATA1 DATA2 Figure 6. Digital Microphone Timing Rev.
ADAU1361 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Power Supply (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range Storage Temperature Range Rating −0.3 V to +3.65 V ±20 mA −0.3 V to AVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
ADAU1361 32 31 30 29 28 27 26 25 SCL/CCLK SDA/COUT ADDR1/CDATA LRCLK BCLK DAC_SDATA ADC_SDATA DGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADAU1361 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 DVDDOUT AVDD AGND MONOOUT LHP RHP LOUTP LOUTN NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1361 GROUNDS. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
ADAU1361 Pin No. 19 20 21 Mnemonic RHP LHP MONOOUT Type 1 A_OUT A_OUT A_OUT 22 AGND PWR 23 AVDD PWR 24 DVDDOUT PWR 25 DGND PWR 26 27 28 29 30 ADC_SDATA DAC_SDATA BCLK LRCLK ADDR1/CDATA D_OUT D_IN D_IO D_IO D_IN 31 SDA/COUT D_IO 32 SCL/CCLK D_IN EP Exposed Pad 1 Description Right Headphone Output. Biased at AVDD/2. Left Headphone Output. Biased at AVDD/2. Mono Output or Virtual Ground for Capless Headphone. Biased at AVDD/2 when set as mono output. Analog Ground.
ADAU1361 28 –30 26 –35 24 –40 22 –45 20 –50 –55 THD + N (dBV) 18 16 14 12 10 –65 –70 –75 –85 6 –90 4 –95 2 –100 –50 –40 –30 –20 –10 0 DIGITAL 1kHz INPUT SIGNAL (dBFS) –105 –60 –50 –40 –30 –20 –10 0 DIGITAL 1kHz INPUT SIGNAL (dBFS) Figure 8. Headphone Amplifier Power vs. Input Level, 16 Ω Load 07679-069 –80 0 –60 Figure 11. Headphone Amplifier THD + N vs.
0.10 −10 0.08 −20 0.06 −30 0.04 −40 −50 −60 −70 0.02 0 −0.02 −0.04 −80 −0.06 −90 −0.08 −100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) −0.10 Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (NORMALIZED TO fS) 07679-011 MAGNITUDE (dBFS) 0 07679-010 MAGNITUDE (dBFS) ADAU1361 Figure 17.
0 0.05 −10 0.04 −20 0.03 −30 0.02 −40 −50 −60 −70 0.01 0 −0.01 −0.02 −80 −0.03 −90 −0.04 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 −0.05 07679-016 −100 1.0 FREQUENCY (NORMALIZED TO fS) Figure 20. DAC Interpolation Filter, 128× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (NORMALIZED TO fS) 07679-017 MAGNITUDE (dBFS) MAGNITUDE (dBFS) ADAU1361 Figure 23.
ADAU1361 SYSTEM BLOCK DIAGRAMS FROM VOLTAGE REGULATOR (1.8V TO 3.3V) 10µF + 0.1µF 10µF 10µF + + 0.1µF 0.1µF 0.1µF 1.2nH THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE, WHICH VARIES WITH THE VOLUME SETTING. DVDDOUT IOVDD AVDD 9.
ADAU1361 FROM VOLTAGE REGULATOR (1.8V TO 3.3V) 10µF + 0.1µF 10µF 10µF + + 0.1µF 0.1µF 0.1µF 1.2nH THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE, WHICH VARIES WITH THE VOLUME SETTING. DVDDOUT IOVDD AVDD 9.
ADAU1361 FROM VOLTAGE REGULATOR (1.8V TO 3.3V) 10µF + 0.1µF 10µF 10µF + + 0.1µF 0.1µF 0.1µF 1.2nH DVDDOUT IOVDD AVDD 9.1pF CAPLESS HEADPHONE OUTPUT AVDD MICBIAS RHP BCLK 2.5V TO 5.0V MONOOUT CLK CM DIGITAL MICROPHONE VDD LHP LINP 10µF LINN DATA 0.1µF 0.1µF RINN L/R SELECT 22nF GND RINP 22nF BCLK VDD REXT INL– 22nF REXT 22nF REXT ROUTP DIGITAL MICROPHONE ROUTN DATA SSM2306 OUTL+ OUTL– CLASS-D 2W STEREO SPEAKER DRIVER INR+ OUTR+ OUTR– INR– SD 0.
ADAU1361 THEORY OF OPERATION The ADAU1361 is an audio codec that offers high quality audio, low power, and small package size. The stereo ADC and stereo DAC each have an SNR of at least +98 dB and a THD + N of at least −90 dB. The serial data port is compatible with I2S, leftjustified, right-justified, and TDM modes for interfacing to digital audio data. The operating voltage range is 1.8 V to 3.65 V, with an on-board regulator generating the internal digital supply voltage.
ADAU1361 STARTUP, INITIALIZATION, AND POWER This section describes the procedure for properly starting up the ADAU1361. The following sequence provides a high level approach to the proper initiation of the system. 1. 2. 3. 4. POWER REDUCTION MODES Sections of the ADAU1361 chip can be turned on and off as needed to reduce power consumption. These include the ADCs, the DACs, and the PLL. Apply power to the ADAU1361. Lock the PLL to the input clock (if using the PLL). Enable the core clock.
ADAU1361 Case 2: PLL Is Used The core clock to the entire chip is off during the PLL lock acquisition period. The user can poll the lock bit to determine when the PLL has locked. After lock is acquired, the ADAU1361 can be started by asserting the core clock enable bit (COREN) in Register R0 (clock control register, Address 0x4000). This bit enables the core clock to all the internal blocks of the ADAU1361.
ADAU1361 CLOCKING AND SAMPLING RATES CLKSRC CORE CLOCK SERIAL DATA INPUT/OUTPUT PORT CONVSR[2:0] fS/0.5, 1, 1.5, 2, 3, 4, 6 DAC_SDATA INFREQ[1:0] 256 × fS, 512 × fS, 768 × fS, 1024 × fS DACs 07679-020 × (R + N/M) ADCs BCLK ÷X R17: CONVERTER CONTROL 0 REGISTER LRCLK MCLK R0: CLOCK CONTROL REGISTER ADC_SDATA R1: PLL CONTROL REGISTER Figure 29. Clock Tree Diagram CORE CLOCK SAMPLING RATES Clocks for the converters and serial ports are derived from the core clock.
ADAU1361 PLL Fractional Mode The PLL uses the MCLK as a reference to generate the core clock. PLL settings are set in Register R1 (PLL control register, Address 0x4002). Depending on the MCLK frequency, the PLL must be set for either integer or fractional mode. The PLL can accept input frequencies in the range of 8 MHz to 27 MHz. Fractional mode is used when the MCLK is a fractional (R + (N/M)) multiple of the PLL output.
ADAU1361 Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × fS) MCLK Input (MHz) 8 12 13 14.4 19.2 19.68 19.
ADAU1361 RECORD SIGNAL PATH MICIN LEFT DIGITAL MICROPHONE INTERFACE JACKDET/MICIN MICIN RIGHT LINNG[2:0] MIXER 1 (LEFT RECORD MIXER) –12dB TO +6dB PGA LDBOOST[1:0] LINN –12dB TO +35.
ADAU1361 Analog Microphone Inputs Analog Line Inputs For microphone inputs, configure the part in either stereo pseudo-differential mode or stereo full differential mode. Line input signals can be accepted by any analog input.
ADAU1361 Digital Microphone Input ANALOG-TO-DIGITAL CONVERTERS When using a digital microphone connected to the JACKDET/ MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008) must be set to 10 to enable the microphone input and disable the jack detection function. The ADAU1361 must operate in master mode and source BCLK to the input clock of the digital microphone.
ADAU1361 AUTOMATIC LEVEL CONTROL (ALC) • The ADAU1361 contains a hardware automatic level control (ALC). The ALC is designed to continuously adjust the PGA gain to keep the recording volume constant as the input level varies. For optimal noise performance, the ALC uses the analog PGA to adjust the gain instead of using a digital method. This ensures that the ADC noise is not amplified at low signal levels. Extremely small gain step sizes are used to ensure high audio quality during gain changes.
ADAU1361 the threshold for 250 ms before the noise gate operates. Hysteresis is used so that the threshold for coming out of the mute state is 6 dB higher than the threshold for going into the mute state. There are four operating modes for the noise gate. INPUT Noise Gate Mode 0 (see Figure 39) is selected by setting the NGTYP[1:0] bits to 00. In this mode, the current state of the PGA gain is held at its current state when the noise gate logic is activated.
ADAU1361 Noise Gate Mode 3 (see Figure 42) is selected by setting the NGTYP[1:0] bits to 11. This mode is the same as Mode 2 except that at the end of the PGA fade gain interval, a digital mute is performed. In general, this mode is the best-sounding mode, because the audible effect of the digital hard mute is reduced by the fact that the gain has already faded to a low level before the mute occurs. Noise Gate Mode 2 (see Figure 41) is selected by setting the NGTYP[1:0] bits to 10.
ADAU1361 PLAYBACK SIGNAL PATH MX3G1[3:0] LEFT INPUT MIXER –15dB TO +6dB MX3G2[3:0] RIGHT INPUT MIXER MIXER 3 (LEFT PLAYBACK MIXER) –15dB TO +6dB MX3AUXG[3:0] LHPVOL[5:0] LAUX LHP –15dB TO +6dB MIXER 5 (LEFT L/R PLAYBACK MIXER) LEFT DAC –57dB TO +6dB LOUTVOL[5:0] LOUTP MX3LM –57dB TO +6dB MX5G3[1:0] RIGHT DAC MX3RM –1 MX6G3[1:0] LOUTN MONOVOL[5:0] MX7[1:0] MIXER 7 (MONO MIXER) MONOOUT –57dB TO +6dB –1 MX4G1[3:0] MIXER 6 (RIGHT L/R PLAYBACK MIXER) LEFT INPUT MIXER –15dB TO +6dB MX5G4[1:0] MX
ADAU1361 HEADPHONE OUTPUT Headphone Output Power-Up/Power-Down Sequencing The LHP and RHP pins can be driven by either a line output driver or a headphone driver by setting the HPMODE bit in Register R30 (playback headphone right volume control register, Address 0x4024). The headphone outputs can drive a load of at least 16 Ω. To prevent pops when turning on the headphone outputs, the user must wait at least 4 ms to unmute these outputs after enabling the headphone output with the HPMODE bit.
ADAU1361 Jack Detection LINE OUTPUTS When the JACKDET/MICIN pin is set to the jack detect function, a flag on this pin can be used to mute the line outputs when headphones are plugged into the jack. This pin can be configured in Register R2 (digital microphone/jack detection control register, Address 0x4008). The JDFUNC[1:0] bits set the functionality of the JACKDET/MICIN pin. The line output pins (LOUTP, LOUTN, ROUTP, and ROUTN) can be used to drive both differential and single-ended loads.
ADAU1361 CONTROL PORTS The ADAU1361 can operate in one of two control modes: • • 2 I C control SPI control The ADAU1361 has both a 4-wire SPI control port and a 2-wire I2C bus control port. Both ports can be used to set the registers. The part defaults to I2C mode, but it can be put into SPI control mode by pulling the CLATCH pin low three times. The control port is capable of full read/write operation for all addressable registers.
ADAU1361 or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADAU1361 does not issue an acknowledge and returns to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master will write information to the peripheral, whereas a Logic 1 means that the master will read information from the peripheral after writing the subaddress and repeating the start address.
ADAU1361 I2C Read and Write Operations This causes the ADAU1361 SDA to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1361. Figure 50 shows the format of a single-word write operation. Every ninth clock pulse, the ADAU1361 issues an acknowledge by pulling SDA low. Figure 53 shows the format of a burst mode read sequence. This figure shows an example of a read from sequential single-byte registers.
ADAU1361 SPI PORT Chip Address R/W 2 By default, the ADAU1361 is in I C mode, but it can be put into SPI control mode by pulling CLATCH low three times. This is done by performing three dummy writes to the SPI port (the ADAU1361 does not acknowledge these three writes). Beginning with the fourth SPI write, data can be written to or read from the IC. The ADAU1361 can be taken out of SPI mode only by a full reset initiated by power-cycling the IC.
ADAU1361 SERIAL DATA INPUT/OUTPUT PORTS If the PLL of the ADAU1361 is not used, the serial data clocks must be synchronous with the ADAU1361 master clock input. The LRCLK and BCLK pins are used to clock both the serial input and output ports. The ADAU1361 can be set as the master or the slave in a system. Because there is only one set of serial data clocks, the input and output ports must always be both master or both slave.
ADAU1361 LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB LSB MSB 07679-040 SDATA 1/fS 2 Figure 57. I S Mode—16 Bits to 24 Bits per Channel MSB LSB MSB LSB 07679-041 SDATA RIGHT CHANNEL LEFT CHANNEL LRCLK BCLK 1/fS Figure 58. Left-Justified Mode—16 Bits to 24 Bits per Channel RIGHT CHANNEL SDATA MSB LSB MSB LSB 07679-042 LEFT CHANNEL LRCLK BCLK 1/fS Figure 59.
ADAU1361 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS GROUNDING Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 100 nF capacitor. The connections to each side of the capacitor should be as short as possible, and the trace should stay on a single layer with no vias.
ADAU1361 CONTROL REGISTERS Table 26.
ADAU1361 CONTROL REGISTER DETAILS All registers except for the PLL control register are 1-byte write and read registers. R0: Clock Control, 16,384 (0x4000) Bit 7 Bit 6 Bit 5 Reserved Bit 4 Bit 3 CLKSRC Bit 2 Bit 1 INFREQ[1:0] Bit 0 COREN Table 27. Clock Control Register Bits 3 Bit Name CLKSRC [2:1] INFREQ[1:0] 0 COREN Description Clock source select. 0 = direct from MCLK pin (default). 1 = PLL clock. Input clock frequency. Sets the core clock rate that generates the core clock.
ADAU1361 Byte 4 Bits [6:3] Bit Name R[3:0] 4 [2:1] X[1:0] 4 0 Type 5 1 Lock 5 0 PLLEN Description PLL integer setting. Setting Value of R 0010 2 (default) 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 PLL input clock divider. Setting Value of X 00 1 (default) 01 2 10 3 11 4 Type of PLL. When set to integer mode, the values of M and N are ignored. 0 = integer (default). 1 = fractional. PLL lock. This read-only bit is flagged when the PLL has finished locking. 0 = PLL unlocked (default).
ADAU1361 R3: Record Power Management, 16,393 (0x4009) This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADCs, record path mixers, and PGAs can be set to one of four modes. These settings are normal operation, power saving mode, enhanced performance mode, and extreme power saving mode. Each of these modes draws current from a central bias.
ADAU1361 R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1. Bit 7 Reserved Bit 6 Bit 5 LINPG[2:0] Bit 4 Bit 3 Bit 2 LINNG[2:0] Table 31. Record Mixer Left (Mixer 1) Control 0 Register Bits [6:4] Bit Name LINPG[2:0] [3:1] LINNG[2:0] 0 MX1EN Description Gain for a left channel single-ended input from the LINP pin, input to Mixer 1.
ADAU1361 R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) This register controls the gain boost of the left channel differential PGA input and the gain for the left channel auxiliary input in the record path. The left channel record mixer is referred to as Mixer 1. Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 LDBOOST[1:0] Bit 2 Bit 1 MX1AUXG[2:0] Bit 0 Table 32.
ADAU1361 R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) This register controls the gain of single-ended inputs for the right channel record path. The right channel record mixer is referred to as Mixer 2. Bit 7 Reserved Bit 6 Bit 5 RINPG[2:0] Bit 4 Bit 3 Bit 2 RINNG[2:0] Bit 1 Table 33. Record Mixer Right (Mixer 2) Control 0 Register Bits [6:4] Bit Name RINPG[2:0] [3:1] RINNG[2:0] 0 MX2EN Description Gain for a right channel single-ended input from the RINP pin, input to Mixer 2.
ADAU1361 R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) This register controls the gain boost of the right channel differential PGA input and the gain for the right channel auxiliary input in the record path. The right channel record mixer is referred to as Mixer 2. Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 RDBOOST[1:0] Bit 2 Bit 1 MX2AUXG[2:0] Bit 0 Table 34.
ADAU1361 R9: Right Differential Input Volume Control, 16,399 (0x400F) This register enables the differential path and sets the volume control for the right differential PGA input. Bit 7 Bit 6 Bit 5 Bit 4 RDVOL[5:0] Bit 3 Bit 2 Bit 1 RDMUTE Bit 0 RDEN Table 36. Right Differential Input Volume Control Register Bits [7:2] Bit Name RDVOL[5:0] 1 RDMUTE 0 RDEN Description Right channel differential PGA input volume control.
ADAU1361 R11: ALC Control 0, 16,401 (0x4011) Bit 7 Bit 6 PGASLEW[1:0] Bit 5 Bit 4 ALCMAX[2:0] Bit 3 Bit 2 Bit 1 ALCSEL[2:0] Bit 0 Table 38. ALC Control 0 Register Bits [7:6] Bit Name PGASLEW[1:0] [5:3] ALCMAX[2:0] [2:0] ALCSEL[2:0] Description PGA volume slew time when the ALC is off.
ADAU1361 R12: ALC Control 1, 16,402 (0x4012) Bit 7 Bit 6 Bit 5 ALCHOLD[3:0] Bit 4 Bit 3 Bit 2 Bit 1 ALCTARG[3:0] Bit 0 Table 39. ALC Control 1 Register Bits [7:4] Bit Name ALCHOLD[3:0] [3:0] ALCTARG[3:0] Description ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before increasing the gain to achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent distortion of low frequency signals.
ADAU1361 R13: ALC Control 2, 16,403 (0x4013) Bit 7 Bit 6 Bit 5 ALCATCK[3:0] Bit 4 Bit 3 Bit 2 Bit 1 ALCDEC[3:0] Bit 0 Table 40. ALC Control 2 Register Bits [7:4] Bit Name ALCATCK[3:0] [3:0] ALCDEC[3:0] Description ALC attack time. The attack time sets how fast the ALC starts attenuating after an increase in input level above the target. A typical setting for music recording is 384 ms, and a typical setting for voice recording is 24 ms.
ADAU1361 R14: ALC Control 3, 16,404 (0x4014) Bit 7 Bit 6 NGTYP[1:0] Bit 5 NGEN Bit 4 Bit 3 Bit 2 NGTHR[4:0] Bit 1 Bit 0 Table 41. ALC Control 3 Register Bits [7:6] Bit Name NGTYP[1:0] 5 NGEN [4:0] NGTHR[4:0] Description Noise gate type. When the input signal falls below the threshold for 250 ms, the noise gate can hold a constant PGA gain, mute the ADC output, fade the PGA gain to the minimum gain value, or fade then mute.
ADAU1361 R16: Serial Port Control 1, 16,406 (0x4016) Bit 7 Bit 6 BPF[2:0] Bit 5 Bit 4 ADTDM Bit 3 DATDM Table 43. Serial Port Control 1 Register Bits [7:5] Bit Name BPF[2:0] 4 ADTDM 3 DATDM 2 MSBP [1:0] LRDEL[1:0] Description Number of bit clock cycles per LRCLK audio frame. Setting Bit Clock Cycles 000 64 (default) 001 32 010 48 011 128 100 Reserved Reserved 101 110 Reserved 111 Reserved ADC serial audio data channel position in TDM mode. 0 = left first (default). 1 = right first.
ADAU1361 R17: Converter Control 0, 16,407 (0x4017) Bit 7 Reserved Bit 6 Bit 5 DAPAIR[1:0] Bit 4 DAOSR Bit 3 ADOSR Bit 2 Bit 1 CONVSR[2:0] Bit 0 Table 44. Converter Control 0 Register Bits [6:5] Bit Name DAPAIR[1:0] 4 DAOSR 3 ADOSR [2:0] CONVSR[2:0] Description On-chip DAC serial data selection in TDM mode. Setting Pair 00 First pair (default) 01 Second pair 10 Third pair 11 Fourth pair DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
ADAU1361 R19: ADC Control, 16,409 (0x4019) Bit 7 Reserved Bit 6 ADCPOL Bit 5 HPF Bit 4 DMPOL Bit 3 DMSW Bit 2 INSEL Bit 1 Bit 0 ADCEN[1:0] Table 46. ADC Control Register Bits 6 Bit Name ADCPOL 5 HPF 4 DMPOL 3 DMSW 2 INSEL [1:0] ADCEN[1:0] Description Invert input polarity. 0 = normal (default). 1 = inverted. ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz. 0 = off (default). 1 = on. Digital microphone data polarity swap. 0 = invert polarity. 1 = normal (default).
ADAU1361 R21: Right Input Digital Volume, 16,411 (0x401B) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RADVOL[7:0] Bit 2 Bit 1 Bit 0 Table 48. Right Input Digital Volume Register Bits [7:0] Bit Name RADVOL[7:0] Description Controls the digital volume attenuation for right channel inputs from either the right ADC or the right digital microphone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 73 for a complete list of the volume settings.
ADAU1361 R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) Bit 7 Bit 6 Bit 5 MX3G2[3:0] Bit 4 Bit 3 Bit 2 Bit 1 MX3G1[3:0] Bit 0 Table 50. Playback Mixer Left (Mixer 3) Control 1 Register Bits [7:4] Bit Name MX3G2[3:0] [3:0] MX3G1[3:0] Description Bypass gain control. The signal from the right channel record mixer (Mixer 2) bypasses the converters and gain can be applied before the left playback mixer (Mixer 3).
ADAU1361 R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) Bit 7 Reserved Bit 6 MX4RM Bit 5 MX4LM Bit 4 Bit 3 Bit 2 MX4AUXG[3:0] Bit 1 Bit 0 MX4EN Table 51. Playback Mixer Right (Mixer 4) Control 0 Register Bits 6 Bit Name MX4RM 5 MX4LM [4:1] MX4AUXG[3:0] 0 MX4EN Description Mixer input mute. Mutes the right DAC input to the right channel playback mixer (Mixer 4). 0 = muted (default). 1 = unmuted. Mixer input mute.
ADAU1361 R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) Bit 7 Bit 6 Bit 5 MX4G2[3:0] Bit 4 Bit 3 Bit 2 Bit 1 MX4G1[3:0] Bit 0 Table 52. Playback Mixer Right (Mixer 4) Control 1 Register Bits [7:4] Bit Name MX4G2[3:0] [3:0] MX4G1[3:0] Description Bypass gain control. The signal from the right channel record mixer (Mixer 2) bypasses the converters and gain can be applied before the right playback mixer (Mixer 4).
ADAU1361 R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) Bit 7 Bit 6 Reserved Bit 5 Bit 4 Bit 3 MX5G4[1:0] Bit 2 Bit 1 MX5G3[1:0] Bit 0 MX5EN Table 53. Playback L/R Mixer Left (Mixer 5) Line Output Control Register Bits [4:3] Bit Name MX5G4[1:0] [2:1] MX5G3[1:0] 0 MX5EN Description Mixer input gain boost. The signal from the right channel playback mixer (Mixer 4) can be enabled and boosted in the playback L/R mixer left (Mixer 5).
ADAU1361 R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) Bit 7 Bit 6 Bit 5 Reserved Bit 4 Bit 3 Bit 2 Bit 1 MX7[1:0] Bit 0 MX7EN Table 55. Playback L/R Mixer Mono Output (Mixer 7) Control Register Bits [2:1] Bit Name MX7[1:0] 0 MX7EN Description L/R mono playback mixer (Mixer 7). Mixes the left and right playback mixers (Mixer 3 and Mixer 4) with either a 0 dB or 6 dB gain boost.
ADAU1361 R30: Playback Headphone Right Volume Control, 16,420 (0x4024) Bit 7 Bit 6 Bit 5 Bit 4 RHPVOL[5:0] Bit 3 Bit 2 Bit 1 RHPM Bit 0 HPMODE Table 57. Playback Headphone Right Volume Control Register Bits [7:2] Bit Name RHPVOL[5:0] 1 RHPM 0 HPMODE Description Headphone volume control for right channel, RHP output. Each 1-bit step corresponds to a 1 dB increase in volume. See Table 74 for a complete list of the volume settings.
ADAU1361 R32: Playback Line Output Right Volume Control, 16,422 (0x4026) Bit 7 Bit 6 Bit 5 Bit 4 ROUTVOL[5:0] Bit 3 Bit 2 Bit 1 ROUTM Bit 0 ROMODE Table 59. Playback Line Output Right Volume Control Register Bits [7:2] Bit Name ROUTVOL[5:0] 1 ROUTM 0 ROMODE Description Line output volume control for right channel, ROUTN and ROUTP outputs. Each 1-bit step corresponds to a 1 dB increase in volume. See Table 74 for a complete list of the volume settings.
ADAU1361 R34: Playback Pop/Click Suppression, 16,424 (0x4028) Bit 7 Bit 6 Reserved Bit 5 Bit 4 POPMODE Bit 3 POPLESS Bit 2 Bit 1 ASLEW[1:0] Bit 0 Reserved Table 61. Playback Pop/Click Suppression Register Bits 4 Bit Name POPMODE 3 POPLESS [2:1] ASLEW[1:0] Description Pop suppression circuit power saving mode. The pop suppression circuits charge faster in normal operation; however, after they are charged, they can be put into low power operation. 0 = normal (default). 1 = low power.
ADAU1361 R36: DAC Control 0, 16,426 (0x402A) Bit 7 Bit 6 DACMONO[1:0] Bit 5 DACPOL Bit 4 Bit 3 Reserved Bit 2 DEMPH Bit 1 Bit 0 DACEN[1:0] Table 63. DAC Control 0 Register Bits [7:6] Bit Name DACMONO[1:0] 5 DACPOL 2 DEMPH [1:0] DACEN[1:0] Description DAC mono mode. The DAC channels can be set to mono mode within the DAC and output on the left channel, the right channel, or both channels.
ADAU1361 R38: DAC Control 2, 16,428 (0x402C) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 RDAVOL[7:0] Bit 2 Bit 1 Bit 0 Table 65. DAC Control 2 Register Bits [7:0] Bit Name RDAVOL[7:0] Description Controls the digital volume attenuation for right channel inputs from the right DAC. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 73 for a complete list of the volume settings. Setting Volume Attenuation 00000000 0 dB (default) 00000001 −0.375 dB 00000010 −0.75 dB … … 11111110 −95.
ADAU1361 R40: Control Port Pad Control 0, 16,431 (0x402F) The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the control port signals to a defined state when the signal source becomes three-state. Bit 7 Bit 6 CDATP[1:0] Bit 5 Bit 4 CLCHP[1:0] Bit 3 Bit 2 SCLP[1:0] Bit 1 Bit 0 SDAP[1:0] Table 67.
ADAU1361 R42: Jack Detect Pin Control, 16,433 (0x4031) With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively. With IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The optional pull-up/ pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to a defined state when the signal source becomes three-state.
ADAU1361 Table 71. R8 and R9 Volume Settings Binary Value 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 Volume Setting (dB) −12 −11.25 −10.5 −9.75 −9 −8.25 −7.5 −6.75 −6 −5.25 −4.5 −3.75 −3 −2.25 −1.
ADAU1361 Table 73.
ADAU1361 Binary Value 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 01101110 01101111 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 Volume Attenuation (dB) −36 −36.375 −36.75 −37.
ADAU1361 Binary Value 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 11010000 11010001 11010010 11010011 11010100 11010101 11010110 11010111 11011000 11011001 11011010 11011011 11011100 11011101 11011110 11011111 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001 11101010 11101011 11101100 11101101 11101110 11101111 11110000 11110001 11110010 Volume Attenuation (dB) −72.75 −73.125 −73.
ADAU1361 Binary Value 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Volume Setting (dB) −24 −23 −22 −21 −20 −19 −18 −17 −16 −15 −14 −13 −12 −11 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 Rev.
ADAU1361 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 17 16 0.30 0.23 0.18 3.65 3.50 SQ 3.35 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 1 EXPOSED PAD (BOTTOM VIEW) 0.80 MAX 0.65 TYP 12° MAX 32 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 100608-A TOP VIEW 1.00 0.85 0.
ADAU1361 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07679-0-9/10(C) Rev.
