Datasheet

Data Sheet ADAU1328
Rev. B | Page 7 of 32
Parameter Condition Comments Min Max Unit
SPI PORT See Figure 11
t
CCH
CCLK high 35 ns
t
CCL
CCLK low 35 ns
f
CCLK
CCLK frequency f
CCLK
= 1/t
CCP
, only t
CCP
shown in Figure 11 10 MHz
t
CDS
CDATA setup
To CCLK rising
10
ns
t
CDH
CDATA hold From CCLK rising 10 ns
t
CLS
CLATCH
setup To CCLK rising 10 ns
t
CLH
CLATCH
hold From CCLK rising 10 ns
t
CLHIGH
CLATCH
high Not shown in Figure 11 10 ns
t
COE
COUT enable From CCLK falling 30 ns
t
COD
COUT delay From CCLK falling 30 ns
t
COH
COUT hold From CCLK falling, not shown in Figure 11 30 ns
t
COTS
COUT tri-state From CCLK falling 30 ns
DAC SERIAL PORT
See Figure 24
t
DBH
DBCLK high Slave mode 10 ns
t
DBL
DBCLK low Slave mode 10 ns
t
DLS
DLRCLK setup To DBCLK rising, slave mode 10 ns
t
DLH
DLRCLK hold From DBCLK rising, slave mode 5 ns
t
DLS
DLRCLK skew
From DBCLK falling, master mode
−8
+8
ns
t
DDS
DSDATA setup To DBCLK rising 10 ns
t
DDH
DSDATA hold From DBCLK rising 5 ns
ADC SERIAL PORT See Figure 25
t
ABH
ABCLK high Slave mode 10 ns
t
ABL
ABCLK low Slave mode 10 ns
t
ALS
ALRCLK setup To ABCLK rising, slave mode 10 ns
t
ALH
ALRCLK hold From ABCLK rising, slave mode 5 ns
t
ALS
ALRCLK skew From ABCLK falling, master mode −8 +8 ns
t
ABDD
ASDATA delay From ABCLK falling 18 ns
AUXILIARY INTERFACE
t
AXDS
AAUXDATA setup
To AUXBCLK rising
10
ns
t
AXDH
AAUXDATA hold From AUXBCLK rising 5 ns
t
DXDD
DAUXDATA delay From AUXBCLK falling 18 ns
t
XBH
AUXBCLK high 10 ns
t
XBL
AUXBCLK low 10 ns
t
DLS
AUXLRCLK setup To AUXBCLK rising 10 ns
t
DLH
AUXLRCLK hold From AUXBCLK rising 5 ns