Datasheet

ADAU1328 Data Sheet
Rev. B | Page 22 of 32
DBCLK
DLRCLK
DSDATA
LEFT-JUSTIFIED
MODE
DSDATA
RIGHT-JUSTIFIED
MODE
DSDATA
I
2
S-JUSTIFIED
MODE
t
DLH
t
DBH
t
DBL
t
DLS
t
DDS
MSB
MSB
MSB
LSB
MSB–1
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDH
t
DDS
06102-014
Figure 24. DAC Serial Timing
ABCLK
ALRCLK
ASDATA
LEFT-JUSTIFIED
MODE
ASDATA
RIGHT-JUSTIFIED
MODE
ASDATA
I
2
S-JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB
MSB–1
t
ABL
t
ALS
t
ABDD
t
ABDD
t
ABDD
t
ALH
06102-015
Figure 25. ADC Serial Timing