Datasheet

ADAU1328 Data Sheet
Rev. B | Page 20 of 32
DLRCLK
DBCLK
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN)
DAC L1 DAC R1
DAC L2
DAC R2 DAC L1
DAC R1 DAC L2
DAC R2
DSDATA3
(IN)
DAC L3
DAC R3 DAC L4
DAC R4
DAC L3 DAC R3
DAC L4 DAC R4
DSDATA2
(OUT)
DAC L1
DAC R1 DAC L2
DAC R2
DSDATA4
(OUT)
DAC L3
DAC R3 DAC L4
DAC R4
32 BITS
DSP
SECOND
ADAU1328
FIRST
ADAU1328
MSB
06102-055
Figure 19. Dual-Line DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two ADAU1328 Daisy Chain); DSDATA3 and DSDATA4 Are the Daisy Chain
DLRCLK
DBCLK
DSDATA1
DAC L1
DAC R1 DAC L2 DAC R2
DSDATA2
DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
MSB
06102-058
Figure 20. Dual-Line DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
ALRCLK
ABCLK
ASDATA2 (TDM_IN
OF THE SECOND ADAU1328
IN THE CHAIN)
ADC L1 ADC R1 ADC L2 ADC R2
4 ADC CHANNELS OF FIRST IC IN THE CHAIN4 ADC CHANNELS OF SECOND IC IN THE CHAIN
ASDATA1 (TDM_OUT
OF THE SECOND ADAU1328
IN THE CHAIN)
ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2
32 BITS
MSB
DSP
SECOND
ADAU1328
FIRST
ADAU1328
06102-056
Figure 21. Dual-Line ADC TDM Daisy-Chain Mode (256 f
S
ABCLK, Two ADAU1328 Daisy Chain)