Datasheet

ADAU1328 Data Sheet
Rev. B | Page 14 of 32
To maintain the highest performance possible, it is recommended
that the clock jitter of the internal master clock signal be limited
to less than 300 ps rms time interval error (TIE). Even at these
levels, extra noise or tones can appear in the DAC outputs if the
jitter spectrum contains large spectral peaks. If the internal PLL
is not being used, it is highly recommended that an independent
crystal oscillator generate the master clock. In addition, it is
especially important that the clock signal not be passed through
an FPGA, CPLD, or other large digital chip (such as a DSP)
before being applied to the ADAU1328. In most cases, this
induces clock jitter due to the sharing of common power and
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
Reset sets all the control registers to their default settings. To
avoid pops, reset does not power down the analog outputs.
After reset is deasserted, and the PLL acquires lock condition,
an initialization routine runs inside the ADAU1328. This
initialization lasts for approximately 256 MCLKs.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained.
The reset pin should be pulled low by an external resistor to
guarantee proper startup.
SERIAL CONTROL PORT
The ADAU1328 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. A standalone mode is available for
operation without serial control, standalone is configured at
reset by connecting CIN, CCLK and
CLATCH
to ground. In
standalone mode, all registers are set to default, except the internal
MCLK enable which is set to 1. The ADC ABCLK and ALRCLK
clock ports are set to master/slave by the connecting the COUT
pin to either DVDD or ground. Standalone mode only supports
stereo mode with an I
2
S data format and 256 f
S
MCLK rate. Refer
to Table 10 for details. If CIN, CCLK, and
CLATCH
are not
grounded, the ADAU1328 SPI port is active. It is recommended
to use a weak pull-up resistor on
CLATCH
in applications that
have a microcontroller. This pull-up resistor ensures that the
ADAU1328 recognizes the presence of a microcontroller.
The SPI control port of the ADAU1328 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
ADAU1328, the address is 0x04, shifted left 1 bit due to the
R/
W
bit. The second byte is the ADAU1328 register address
and the third byte is the data.
Table 10. Standalone Mode Selection
ADC Clocks CIN/ADR0 COUT/SDA CCLK/SCL
CLATCH
/ADR1
Slave 0 0 0 0
Master 0 1 0 0
D0
D0
D8
D8
D22D23
D9
D9
CLATCH
CCLK
CIN
COUT
t
CCH
t
CCL
t
CDS
t
CDH
t
CLS
t
CCP
t
CLH
t
COTS
t
COD
t
COE
06102-010
Figure 11. Format of SPI Signal