Datasheet

ADAU1328 Data Sheet
Rev. B | Page 10 of 32
Pin No. In/Out Mnemonic Description
23 I CIN/ADR0 Control Data Input (SPI).
24 I/O COUT/SDA Control Data Output (SPI).
25 I DGND Digital Ground.
26 I CCLK/SCL Control Clock Input (SPI).
27
I
CLATCH
/ADR1
Latch Input for Control Data (SPI).
28 O OL1 DAC 1 Left Output.
29 O OR1 DAC 1 Right Output.
30 O OL2 DAC 2 Left Output.
31 O OR2 DAC 2 Right Output.
32 I AGND Analog Ground.
33
I
AVDD
Analog Power Supply. Connect to analog 3.3 V supply.
34 I AGND Analog Ground.
35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
36 I AGND Analog Ground.
37 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
38
O
CM
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 µF||100 nF to AGND.
39 I ADC1LP ADC1 Left Positive Input.
40 I ADC1LN ADC1 Left Negative Input.
41 I ADC1RP ADC1 Right Positive Input.
42 I ADC1RN ADC1 Right Negative Input.
43 I ADC2LP ADC2 Left Positive Input.
44 I ADC2LN ADC2 Left Negative Input.
45 I ADC2RP ADC2 Right Positive Input.
46 I ADC2RN ADC2 Right Negative Input.
47 O LF PLL Loop Filter. Return to AVDD.
48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.