Datasheet

ADATE207
Rev. 0 | Page 4 of 36
AC SPECIFICATIONS
T
C
= 85°C ± 5°C, VDD = 2.5 V, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
CLOCK INPUTS
Master Clock (MCLK) Frequency 100 MHz
MCLK Duty Cycle 46 50 54 %
DRIVE OUTPUTS
Output Pulse Width Timing error < ±125 ps 1 ns
COMPARE INPUTS
Minimum Comparison Window Width 1.25 ns
Minimum Detectable Glitch Width 1.25 ns
EDGE PERFORMANCE
Retrigger Time 2.5 ns
Edge Delay 0
Lesser of 4 T0 cycles
or 163.8 μs
Vernier Resolution 39.06 ps
Vernier Timing DNL −150 +150 ps
Vernier Timing INL −150 +150 ps
Vernier Temperature Coefficient 4 ps/°C
Edge Jitter MCLK jitter 5 ps rms 20 ps rms
CONTROL AND STATUS REGISTER (CSR) INTERFACE
Clock Period 10 ns
Setup Time (t
BSU
) MCLK 1.1 ns
Hold Time (t
BH
) MCLK 0.5 ns
Clock to Output (t
BCO
) MCLK 2.5 7.0 ns
Clock to Tristate (t
BCZ
) 2.3 4.2 ns
Clock to Data Valid from Tristate (t
BCZV
) 0 7.0 ns
DIGITAL INPUTS
Set Up (t
ISU
) MCLK 1.7 ns
Hold Time (t
IH
) MCLK 0.5 ns
DIGITAL OUTPUTS
Clock to Output (t
OCO
) MCLK 0.7 1.6 ns
JTAG PORTS
JTAG Clock Period 100 ns
Setup Time (t
SSU
) JTAG CLOCK 50 ns
Hold Time (t
SH
) JTAG CLOCK 50 ns
Clock to Output (t
SCO
) JTAG CLOCK 50 ns