Datasheet

ADATE207
Rev. 0 | Page 23 of 36
Name: Fail Counter High
Address: 0x02
Type: Read/Write
Table 16. Fail Counter High
Position Description Reset State
Bits[15:00]
Fail Counter Data High. This field contains the 16 MSBs of the fail counter. See
Table 15, the fail
counter low register, for more information.
0x0000
Name: Static Configuration
Address: 0x03
Type: Read/Write
Table 17. Static Configuration
Position Description Reset State
Bits[15:04] Not Used. 0x000
Bit 03 Ch_Data_Low. 0
A high with edges disabled produces a low level output from the drive data (DR_DATA) signal
regardless of pattern data.
Pulsing this bit allows the data to be preset to a low level output prior to bursting a pattern.
Control of the drive data is pattern data dependent when a pattern is burst.
If both Data_High and Data_Low are high, the data is indeterminate.
Bit 02 Ch_Data_High. 0
A high with edges disabled produces a high level output from the drive data (DR_DATA) signal
regardless of pattern data
Pulsing this bit allows the data to be preset to a high level output prior to bursting a pattern.
Control of the drive data is pattern data dependent when a pattern is burst.
Bit 01 Ch_Driver_Off. 0
A high with edges disabled produces a low level output from the drive enable (DR_EN) signal,
tristating the driver regardless of pattern data.
Pulsing this bit allows the driver to tristate prior to bursting a pattern.
Control of the driver is pattern data dependent when a pattern is burst.
If both Driver_On and Driver_Off are high, the drive enable signal (DR_EN) is indeterminate.
Bit 00 Ch_Driver_On. 0
A high with edges disabled produces high level output from the drive enable (DR_EN) signal,
enabling the driver regardless of pattern data.
Pulsing this bit enables the driver prior to bursting a pattern.
Control of the driver is pattern data dependent when a pattern is burst.