Datasheet

ADATE207
Rev. 0 | Page 20 of 36
MCLK
CYCLES
RD
CS_AS LOW ENDS BURST
BURST ADDRESS CYCLE INITIATES BURST
CS_AS
CS_RW_B
CS_AD
RABA WD1 WD3WD2 WD4 WD5 WD7WD6 WD8
05557-011
Figure 17. Write Burst Mode Functional Timing
BA
1 CYCLE OF BUS TURN-AROUND1 CYCLE OF BUS TURN-AROUND +
8 CYCLES OF READ DATA DELAY
MCLK
CYCLES
CS_AS
C
S_RW_B
CS_AD
CS_AS LOW ENDS BURST
WD4RD1 RD3RD2 RD4 RD5 RD7RD6 RD8 A4
05557-012
Figure 18. Read Burst Mode Functional Timing
BA WD4RD1 RD2 RD3 RD4 A4
1 CYCLE OF BUS TURN-AROUND
1 CYCLE OF BUS TURN-AROUND +
8 CYCLES OF READ DATA DELAY
MCLK
CYCLES
CS_AS
CS_RW_B
CS_AD
EXTRA CYCLE ASSERTED CAUSES 2 CYCLES OF READ DATA HOLD TIME
CS_AS LOW ENDS BURST
05557-013
Figure 19. Read Burst Mode with Read Data Hold Functional Timing