Datasheet

Data Sheet ADAS3023
CONFIGURATION REGISTER
The configuration register, CFG, is a 16-bit programmable
register for selecting all of the user-programmable options of
the ADAS3023 (see Table 11).
The register is loaded when data is read back for the first
16 SCK rising edges, and it is updated at the next EOC. Note
that there is always a one-deep delay when writing to CFG, and
when reading back from CFG, it is the setting associated with
the current conversion.
The default CFG setting is applied when the ADAS3023 returns
from the reset state (RESET = high) to the operational state
(RESET = low). Returning from the full power-down state
(PD = high) to an enabled state (PD = low), the default CFG
setting is not applied and at least one dummy conversion is
required for the user specified CFG to take effect. To ensure the
digital core is in the default state, apply an external reset after the
deassertion of PD. The default value is CFG[15:0] = 0xFFFF. To
read back the contents of the configuration register, CFG, an
additional 16 SCKs are provided after all of the channel data
have been read, and CFG is made available on the SDO output.
The default CFG settings configure the ADAS3023 as follows:
• Overwrites contents of the CFG register.
• Selects the eight input channels mode.
• Configures the PGIA gain to 0.20 (±20.48 V).
• Enables the internal reference.
• Selects normal conversion mode.
• Disables the SDO2 readout mode.
Table 10. Configuration Register, CFG Bit Map; Default Value = 0xFFFF (1111 1111 1111 1111)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG INx INx RSV PGIA PGIA PGIA PGIA PGIA PGIA PGIA PGIA RSV REFEN CMS BUSY/SDO2
Table 11. Configuration Register Description
Bit No. Bit Name Description
15
CFG
Configuration update.
0 = keeps current configuration settings.
1 = overwrites contents of register.
[14:13]
INx
Selection of the number of channels to be converted simultaneously.
Bit 14
Bit 13
Channels
0
0
2
0
1
4
1 0 6
1 1 8
12 RSV Reserved. Setting or clearing this bit has no effect.
[11:4]
PGIA
Programmable gain selection (see the Programmable Gain section).
Bit (Odd)
Bit (Even)
PGIA Gain
0 0
±10.24 V
0 1
±5.12 V
1 0
±2.56 V
1 1
±20.48 V (default)
[11:10]
PGIA
Sets the gain of IN0.
[9:8] PGIA Sets the gain of IN1.
[7:6] PGIA Sets the gain of IN3 to IN2.
[5:4]
PGIA
Sets the gain of IN4 to IN7.
3
RSV
Reserved. Setting or clearing this bit has no effect.
2
REFEN
Internal reference (see the Pin Configuration and Function Descriptions and Voltage Reference Input/Output sections).
0 = disables the internal reference. Disable the internal reference buffer by pulling REFIN to ground.
1 = enables the internal reference (default).
1 CMS Conversion mode selection (see the Conversion Modes section).
0 = uses the warp mode for conversions with a time between conversion restriction.
1 = uses the normal mode for conversions (default).
0
BUSY/SDO2
Secondary data output control using the BUSY/SDO2 pin.
0 = enables the device busy status when the
CS
pin is held high. On the
CS
falling edge, the MSB of Channel 1 is
presented on the BUSY/SDO2 input and subsequent data is presented on the SCK falling edges.
1 = enables the device busy status only (default). All data is transmitted via the SDO pin on the SCK falling edge.
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