Datasheet
ADAS3023 Data Sheet
GENERAL TIMING
Figure 48 and Figure 49 conversion timing diagrams show the
specific timing parameters, including the complete register to
conversion and readback pipeline delay. These figures detail the
timing from a power up or from returning from a full power
down by use of the PD input. When the BUSY/SDO2 output is
not enabled after the EOC, the data available on the SDO output
(MSB first) can be read after the16 SCK rising edges in sequen-
tial fashion (from Channel 0 (CH0) to Channel 7 (CH7)), as shown
in Figure 48.
The converter busy signal is always output on the BUSY/SDO2
pin when
CS
is logic high. When the BUSY/SDO2 output is ena-
bled when
CS
is brought low after the EOC, the SDO outputs the
data of Channel 0 to Channel 3 (CH0, CH1, CH2, and CH3), and
the SDO2 outputs the data of Channel 4 to Channel 7 (CH4, CH5,
CH6, and CH7) after 16 SCK rising edges, as shown in
Figure 49.
The conversion result output on BUSY/SDO2 pin synchronizes to
the SCK falling edges. The conversion results are in twos comple-
ment format. Reading or writing data during the quiet conversion
phase (t
CONV
) may cause incorrect bit decisions.
Figure 48. General Timing Diagram with BUSY/SDO2 Disabled
Figure 49. General Timing Diagram with BUSY/SDO2 Enabled
1 16 1
16 1
16 1
16 1
16 1 16
PHASE
CNV
SCK
DIN
SDO
BUSY/
SDO2
CS
SOC
SOC
EOC
NOTE 2
NOTE 1
NOTE 4
NOTE 3
NOTE 2
NOTE 1
EOC
POWER
UP
t
CONV
t
CYC
t
CNVH
t
AD
CONVERSION (n) CONVERSION (n + 1)
ACQUISITION (n + 1)
ACQUISITION (n + 2)
SOC
DATA (n)
CFG (n + 2) CFG (n + 3)
CH0 CH1
CH7 CH0 CH1 CH7
DATA (n + 1)
10942-019
t
CBD
NOTES
1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC).
2.
A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED
WITH CONVERSION.
3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL.
4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY,
t
AD
, SHOULD LAPSE PRIOR TO DATA ACCESS.
1 16
PHASE
CNV
SCK
DIN
SDO
BUSY/
SDO2
CS
SOC SOC
EOC
NOTE 1
NOTE 4
NOTE 3
NOTE 2
NOTE 1
EOC
POWER
UP
t
CONV
t
CYC
t
CNVH
t
AD
CONVERSION (n) CONVERSION (n + 1)ACQUISITION (n + 1) ACQUISITION (n + 2)
SOC
DATA (n)
CFG (n + 2) CFG (n + 3)
DATA (n + 1)
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
1 16
1 16 1 16 1 16 1 16 1 16 1 16
10942-020
NOTES
1. DATA ACCESS CAN ONLY OCCUR AFTER CONVERSION. BOTH CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF THE CONVERSION (EOC).
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED FOR CONVERSION RESULT. AN ADDITIONAL 16 EDGES AFTER THE LAST CONVERSION RESULT ON BUSY READS BACK THE CFG ASSOCIATED
WITH CONVERSION.
3. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS IS SHOWN WITH FULL INDEPENDENT CONTROL.
4. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING INSTANT. A MINIMUM TIME OF AT LEAST THE APERATURE DELAY,
t
AD
, SHOULD LAPSE PRIOR TO DATA ACCESS.
Rev. 0 | Page 28 of 32