Datasheet

ADAS3023 Data Sheet
DIGITAL INTERFACE
The ADAS3023 digital interface consists of asynchronous
inputs and a 4-wire serial interface for conversion result
readback and configuration register programming.
This interface uses the three asynchronous signals (CN V, RE SE T,
and PD) and a 4-wire serial interface comprised of
CS
, SDO,
SCK, and DIN.
CS
can also be tied to CNV for some applications.
Conversion results are presented to the serial data output pin
(SDO) after the end of a conversion. The 16-bit configuration
word, CFG, is programmed on the serial data input pin, DIN
during the first 16 SCKs of any data transfer. This CFG register
controls the settings, such as selecting the number of channels to
be converted, the programmable gain settings for each channel
group, and the reference choice (see Configuration Register
section for more information).
CONVERSION CONTROL
The CNV input initiates conversions for N enabled channels as
defined in the CFG register. The ADAS3023 is fully asynchronous
and can perform conversions at any frequency from dc up to
500 kSPS, depending on the settings specified in the configuration
register and the system serial clock rate.
CNV Rising—Start of Conversion (SOC)
A rising edge on the CNV changes the state of the ADAS3023 from
track mode to hold mode, as well as all that is necessary to initiate a
conversion. All conversion clocks are generated internally. After a
conversion is initiated, the ADAS3023 ignores other activity on
the CNV line (governed by the throughput rate) until the end of
the conversion.
While the ADAS3023 is performing a conversion and the BUSY/
SDO2 output is driven high, the ADAS3023 uses a unique 2-phase
conversion process, allowing for safe data access and quiet time.
The CNV signal is decoupled from the
CS
pin, allowing multiple
ADAS3023 devices to be controlled by the same processor. For
applications where SNR is critical, the CNV source requires very
low jitter, which is achieved by using a dedicated oscillator or by
clocking CNV with a high frequency, low jitter clock. For appli-
cations where jitter is more tolerable or a single device is in use, tie
CNV to
CS
. For more information on sample clock jitter and
aperture delay, see the MT-007 Mini Tutorial, Aperture Time,
Aperture Jitter, Aperture Delay Time—Removing the Confusion.
Although CNV is a digital signal, take care to ensure fast, clean
edges with minimal overshoot, undershoot, and ringing. In
addition, avoid digital activity close to the sampling instant because
such activity can result in degraded SNR performance.
BUSY/SDO2 Falling Edge—End of Conversion (EOC)
The EOC is indicated by BUSY/SDO2 returning low and can be
used as a host interrupt. In addition, the EOC gates data access
to and from the ADAS3023. If the conversion result is not read
prior to the next EOC event, the data is lost. Furthermore, if the
CFG update is not completed prior to the EOC, it is discarded and
the current configuration is applied to future conversions. This
pipeline ensures that the ADAS3023 has sufficient time to acquire
the next sample to the specified 16-bit accuracy.
Register Pipeline
The CFG register is written on the first 16 SCKs following the
EOC event, and it is updated on the next EOC event. To ensure
that all CFG updates are applied during a known safe instant to
the various circuit elements, the asynchronous data transfer is
synchronized to the ADAS3023 timing engine using the EOC
event. This synchronization introduces an inherent delay between
updating the CFG register setting and the application of the
configuration to a conversion. This pipeline, from the end of
the current conversion (n), consists of a one-deep delay before
the CFG setting takes effect. This means that two SOC and EOC
events must elapse before the setting (that is, the new channel,
gain, and so forth) takes effect. Note that the nomenclature (n),
(n + 1), and so forth is used in the remainder of the following
digital sections (Serial Data Interface, General Timing, and
Configuration Register) for simplicity. Note, however, that there
is no pipeline after the end of a conversion before data can be
read back.
RESET AND POWER-DOWN (PD) INPUTS
The asynchronous RESET and PD inputs can be used to reset
and power down the ADAS3023, respectively. Timing details
are shown in Figure 46.
F
igure 46. RESET and PD Timing
A rising edge on RESET or PD aborts the conversion process and
places SDO into high impedance, regardless of the
CS
level. Note
that RESET has a minimum pulse width (active high) time for
setting the ADAS3023 into the reset state. See the Configuration
Register section for the default CFG setting when the ADAS3023
returns from the reset state. If this default setting is used after
RESET is deasserted (Logic 0), for the conversion result to be
valid, a period equal to the acquisition time (t
ACQ
) must elapse
before CNV can be asserted; otherwise, if a conversion is
initiated, the result is corrupted. In addition, the output data
from the previous conversion is cleared upon a reset; attempting
10942-017
CS
SDO
CNV
n – 1
UNDEFINED
n
SEE NOTE
SEE NOTE
n – 2
x x
x
BUSY
RESET/
PD
t
DIS
t
EN
t
RH
t
ACQ
t
CCS
CFG
n + 1x
DEFAULT
NOTES
1. WHEN THE PART IS RELEASED FROM RESET,
t
ACQ
MUST BE
MET FOR CONVERSION n IF USING THE DEFAULT CFG
SETTING FOR CHANNEL IN0. WHEN THE PART IS RELEASED
FROM POWER-DOWN,
t
ACQ
IS NOT REQUIRED, AND THE FIRST
TWO CONVERSIONS, n AND n + 1, ARE UNDEFINED.
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