Datasheet

ADAS3023 Data Sheet
Table 7 describes each differential input range and the corre-
sponding LSB size, PGIA bit settings, and PGIA gain.
Table 7. Differential Input Ranges, LSB Size, and PGIA
Settings
Differential Input Ranges,
INx − COM (V) LSB (μV)
PGIA
CFG
PGIA
Gain
(V/V)
±20.48 625 11 0.2
±10.24 312.5 00 0.4
±5.12 156.3 01 0.8
±2.56 78.13 10 1.6
Common-Mode Operating Range
The differential input common-mode range changes according
to the input range selected for a given channel and the high vol-
tage power supplies. Note that the operating input voltage of
any input pin, as defined in the Specifications section, requires
a minimum of 2.5 V of headroom from the VDDH/VSSH
supplies or
(VSSH + 2.5 V) ≤ INx/COM ≤ (VDDH – 2.5 V)
The following sections offer some examples of setting the PGIA
for various input signals. Note that the ADAS3023 always takes
the difference between the INx and COM signals.
Single-Ended Signals with a Nonzero DC Offset
(Asymmetrical)
When a 5.12 V p-p signal with a 2.56 V dc offset is connected to
one of the inputs (INx+) and the dc ground sense of the signal
is connected to COM, the PGIA gain configuration is set to 01
for the ±5.12 V range because the maximum differential voltage
across the inputs is +5.12 V. This scenario uses only half the
codes available for the transfer function.
Figure 40. Typical Single-Ended Unipolar Input Using Only Half of the Codes
Single-Ended Signals with a 0 V DC Offset (Symmetrical)
Compared with the example in the Single-Ended Signals with a
Nonzero DC Offset (Asymmetrical) section, a better solution
for single-ended signals, when possible, is to remove as much
differential dc offset between INx and COM such that the average
voltage is 0 V (symmetrical around the ground sense). The
differential voltage across the inputs is never greater than
±2.56 V, and the PGIA gain configuration is set for a ±2.56 V
range (10). This scenario uses all of the codes available for the
transfer function, making full use of the allowable differential
input range.
Figure 41. Optimal Single-Ended Configuration Using All Codes
Notice that the voltages in the examples are not integer values
due to the 4.096 V reference and the scaling ratios of the PGIA.
The maximum allowed dc offset voltage on the COM input pin
for various PGIA gains in this case is shown in Table 8.
Table 8. DC Offset Voltage on COM Input and PGIA
Settings
1
PGIA Gain (V/V) DC Offset Voltage on COM (V)
0.2 0
0.4 0
0.8 ±5.12
1.6
±7.68
1
Full-scale signal on INx.
VOLTAGE REFERENCE INPUT/OUTPUT
The ADAS3023 allows the choice of an internal reference, an
external reference using an internal buffer, or an external
reference.
The internal reference of the ADAS3023 provides excellent
performance and can be used in nearly any application. Setting
the reference selection mode uses the internal reference enable
bit, REFEN, and the REFIN pin as described in the following
sections (Internal Reference, External Reference and Internal
Buffer, External Reference, and Reference Decoupling).
Internal Reference
The precision internal reference is factory trimmed and is
suitable for most applications.
Setting the REFEN bit in the CFG register to 1 (default) enables
the internal reference and produces 4.096 V on the REF1 and
REF2 pins; this 4.096 V output serves as the main system reference.
The unbuffered 2.5 V (typical) band gap reference voltage is
output on the REFIN pin, which requires an external parallel
combination of 10 μF and 0.1 μF capacitors to reduce the noise
on the output. Because the current output of REFIN is limited,
it can be used as a source when followed by a suitable buffer,
such as the AD8031. Note that excessive loading of the REFIN
output lowers the 4.096 V system reference because the internal
amplifier uses a fixed gain.
The internal reference output is trimmed to the targeted value
of 4.096 V with an initial accuracy of ±8 mV. The reference is
also temperature compensated to provide a typical drift of
±5 ppm/°C.
When the internal reference is used, decouple the ADAS3023,
as shown in Figure 42. Note that both the REF1 and REF2 con-
nections are shorted together and externally decoupled with
ADAS3023
INx+
INx+
+5.12V
5.12V p-p
COM
0V
COM
V
OFF
V
OFF
10942-011
ADAS3023
INx+
INx+
+2.56V
5.12V p-p
COM
–2.56V
COM
0V
10942-012
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