Datasheet

ADAS3023 Data Sheet
Figure 36. System Timing
Regardless of the type of signal, (single-ended symmetric or
asymmetric), the ADAS3023 converts all signals present on the
enabled inputs and COM pin in a differential fashion identical
to an industry-standard difference or instrumentation amplifier.
The conversion results are available after the conversion is complete
and can be read back at any time before the end of the next con-
version. Avoid reading back data during the quiet period, indicated
by BUSY/SDO2 being active high. Because the ADAS3023 has
an on-board conversion clock, the serial clock (SCK) is not
required for the conversion process; it is only required to
present results to the user.
TRANSFER FUNCTIONS
The ideal transfer characteristic for the ADAS3023 is shown in
Figure 37. The inputs are configured for differential input ranges
and the data outputs are in twos complement format, as listed in
Table 6.
Figure 37. ADC Ideal Transfer Function
Table 6. Output Codes and Ideal Input Voltages
Description Differential Analog Inputs, V
REF
= 4.096 V
Digital Output Code
(Twos Complement Hex)
FSR − 1 LSB (32,767 × V
REF
)/(32,768 × PGIA gain) 0x7FFF
Midscale + 1 LSB (V
REF
/(32,768 × PGIA gain)) 0x0001
Midscale 0 0x0000
Midscale − 1 LSB −(V
REF
/(32,768 × PGIA gain)) 0xFFFF
−FSR + 1 LSB
−(32,767 × V
REF
)/(32,768 × PGIA gain)
0x8001
−FSR −V
REF
× PGIA gain 0x8000
CNV
PHASE
CONVERSION ACQUISITION
t
CYC
t
CONV
t
ACQ
10942-008
100...000
100...001
100...010
011...101
011...110
011...111
TWOS
COMPLEMENT
STRAIGHT
BINARY
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE
ANALOG INPUT
+FSR – 1.5LSB
+FSR – 1LSB
–FSR + 1LSB
–FSR
–FSR + 0.5LSB
10942-009
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