Datasheet

Data Sheet ADAS3022
Rev. B | Page 7 of 40
TIMING SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal reference, V
REF
= 4.096 V,
f
S
= 1 MSPS. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
Time Between Conversions t
CYC
Warp Mode,
1
CMS = 0 1 1000 μs
Normal Mode (Default), CMS = 1 1.1 μs
Conversion Time: CNV Rising Edge to Data Available t
CONV
Warp Mode, CMS = 0 825 ns
Normal Mode (Default), CMS = 1 925 1000 ns
Auxiliary ADC Input Channel Acquisition Time t
ACQ
600 ns
CNV Pulse Width t
CH
10 ns
CNV High to Hold Time (Aperture Delay) t
AD
2 ns
CNV High to Busy Delay t
CBD
520 ns
Safe Data Access Time During Conversion t
DDC
500 ns
Quiet Conversion Time (BUSY High) t
QUIET
Warp Mode, CMS = 0 400 ns
Normal Mode (Default), CMS = 1 500 ns
Data Access During Quiet Conversion Time t
DDCA
Warp Mode, CMS = 0 200 ns
Normal Mode (Default), CMS = 1 300 ns
SCK Period t
SCK
15 ns
SCK Low Time t
SCKL
5 ns
SCK High Time t
SCKH
5 ns
SCK Falling Edge to Data Valid t
SDOH
4 ns
SCK Falling Edge to Data Valid Delay t
SDOD
VIO > 4.5 V 12 ns
VIO > 3.0 V 18 ns
VIO > 2.7 V 24 ns
VIO > 2.3 V 25 ns
VIO > 1.8 V 37 ns
CS
/RESET/PD Low to SDO
t
EN
VIO > 4.5 V 15 ns
VIO > 3.0 V 16 ns
VIO > 2.7 V 18 ns
VIO > 2.3 V 23 ns
VIO > 1.8 V 28 ns
CS
/RESET/PD High to SDO High Impedance
t
DIS
25 ns
DIN Valid Setup Time from SCK Rising Edge t
DINS
4 ns
DIN Valid Hold Time from SCK Rising Edge t
DINH
4 ns
CNV Rising to
CS t
CCS
5 ns
RESET/PD High Pulse t
RH
5 ns
1
Exceeding the maximum time has an effect on the accuracy of the conversion (see the Conversion Modes section).
I
OL
500µA
500µA
I
OH
1.4V
T
OSDO
C
L
50pF
10516-002
Figure 2. Load Circuit for Digital Interface Timing
3
0% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
1
2V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.
2
0.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
10516-003
Figure 3. Voltage Levels for Timing