Datasheet

ADAS3022 Data Sheet
Rev. B | Page 38 of 40
INx and COM Inputs with AUX Inputs (MUX = 0, TEMPB = 1)
To use individual INx channels with reference to COM or pairs
of INx channels with the AUX inputs in a sequence, the MUX
bit must be set to 0 to append the AUX channel to the end of the
sequence (after the channel set in INx is scanned). Note that the
AUX input is a pair, whereas the INx channel can be referenced to
COM or pairs of INx channels. For example, to scan four single
channels and the AUX inputs, set INx to 011, COM to 1, and
MUX to 0, which results in a sequence order of IN0, IN1, IN2,
IN3, AUX, IN0, IN1, IN2, IN3, AUX, and so on.
INx and COM Inputs with Temperature Sensor
(MUX = 1, TEMPB = 0)
To append the temperature sensor conversion to the end of the
input channel sequence, the TEMPB bit must be set low in the
configuration word. Note that the temperature sensor requires
at least 5 µs between conversions. The data is output in straight
binary format.
INx and COM Inputs with AUX Inputs and Temperature
Sensor (MUX = 0, TEMPB = 0)
Both temperature sensor conversions and auxiliary channel
conversions can be appended to the end of the input sequence
by setting the MUX and TEMPB bits in the CFG register. For
example, to scan all input channels with respect to COM, the
temperature sensor, and the auxiliary channel at once, the user
must set INx to 111, COM to 1, MUX to 0, and TEMPB to 0.
The resulting sequence would be IN0, IN1, IN2, IN3, IN4, IN5,
IN6, IN7, temperature sensor, and AUX.
Sequencer Modes
The ADAS3022 has two sequencer modes, which are
configured with the SEQ bits: basic mode and advanced mode.
Basic mode can be used when all channels are configured with
the same PGIA range. Advanced mode allows individual
channel ranges to be programmed using two additional
advanced sequence registers, ASR0 and ASR1. The SEQ bits are
used to enable the sequencer. Setting SEQ to 01, 10, or 11 specifies
which sequencer mode is used. Depending on the mode, basic
or advanced sequencing determines the next data into DIN.
Note that for any sequencer update there exists a two-deep
delay when writing the register for the setting to take effect.
Basic Sequencer Mode (SEQ = 11)
The basic mode is useful for systems that use the same PGIA
range on all channels. In basic sequencer mode, all that is
required is a single CFG word to place the ADAS3022 in an
automatically scanned mode. On the second conversion
following the EOC for sequencer CFG, the sequencer starts.
After the CFG for basic sequence updates, DIN must be held
low for at least the MSB during the data readback or a new CFG
word will update, disabling the sequencer.
Update During Sequence (SEQ = 01)
Some of the CFG settings, such as PGIA and CMS, can be updated
during a sequence. Writing a new CFG word with the appropriate
bits to be changed for the (n + 2) conversion updates the sequencer
from that point; all channels then use, for example, the new PGIA
value. Note that changing bits in INx for the last channel or chang-
ing COM reinitializes the sequencer at the (n + 2) conversion. A
more practical method is to use the advanced sequencer mode as
described in the
Advanced Sequencer Mode (SEQ = 10) section.
Advanced Sequencer Mode (SEQ = 10)
The advanced mode is useful for systems that require different
gains for different individual INx inputs or different pairs of
INx inputs. In this mode, two additional registers are used to
program the various gain settings. After the initial CFG word
enabling the advanced sequencer mode is written, the ADAS3022
expects to receive at least one additional data transfer for the
first advanced sequencer register, ASR0, or both advanced
sequencer registers, depending on how many channels are in the
sequence. Each ASR requires a conversion and a corresponding
EOC to load the data into the device. The user cannot simply
write 48 bits all at once because, as with all CFG word transfers,
only the first 16 bits are latched and updated at EOC.
Note that the PGIA setting for IN0 or IN0/IN1 is written in the
initial CFG register, and if using pairs of INx channels, only
ASR0 is required. After the CFG and the associated advanced
sequencer registers are updated, DIN must be held low for at
least the MSB of subsequent data transfers; otherwise, the
advanced sequencer mode will be aborted.
Table 13. Advanced Sequencer Register 0
Bits Function
15 ASR0 write enable
0 = update ASR0 following CFG for advanced sequencer
1 = enters normal CFG update
[14:11] Reserved
[10:8] PGIA for IN1 or IN2/IN3
7 Reserved
[6:4] PGIA for IN2 or IN4/IN5
3 Reserved
[2:0] PGIA for IN3 or IN6/IN7
Table 14. Advanced Sequencer Register 1
Bits Function
15 ASR1 write enable
0 = update ASR1 following ASR0
1 = enters normal CFG update
[14:12]
PGIA for IN4
11 Reserved
[10:8] PGIA for IN5
7 Reserved
[6:4] PGIA for IN6
3 Reserved
[2:0] PGIA for IN7