Datasheet

ADAS3022 Data Sheet
Rev. B | Page 36 of 40
CONFIGURATION REGISTER
The configuration register, CFG, is a 16-bit, programmable
register for selecting all of the ADAS3022 user-programmable
options (see Table 11). The register is loaded when data is read
back for the first 16 SCK rising edges and is updated at the next
EOC. Note that there is always a two-deep delay (n + 2) when
writing CFG and when reading back CFG for the setting
associated with the current conversion.
The default CFG setting is applied when the ADAS3022 returns
from the reset state (RESET = high) to the operational state
(RESET = low). However, when the ADAS3022 returns from the
full power-down state (PD = high) to an enabled state (PD = low),
the default CFG setting is not applied, and at least two dummy
conversions are required for the user-specified CFG setting to
take effect. Therefore, the default value is CFG[15:0] = 0x8FCF.
This sets the ADAS3022 as follows:
• Overwrites contents of CFG register
• Selects the IN0 input channel referenced to COM
• Configures the PGIA gain to 0.20 (±20.48 V)
• Selects the multiplexer input
• Disables the internal channel sequencer
• Disables the temperature sensor
• Enables the internal reference
• Selects normal conversion mode
• Selects SPI interface mode
Table 10. Configuration Register, CFG; Default Value = 0x8FCF (1000 1111 1100 1111)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG INx INx INx COM RSV PGIA PGIA PGIA MUX SEQ SEQ TEMPB REFEN CMS CPHA
Table 11. Configuration Register Bit Description
Bits Bit Name Description
15 CFG Configuration update.
0 = keep current configuration settings.
1 = overwrite contents of register (default).
[14:12]
INx
Input channel selection in binary fashion. See the Multiplexer section.
Bit 14 Bit 13 Bit 12 Channel
0 0 0 IN0 (default)
… … …
1 1 1 IN7
11 COM IN[7:0] common channel input. AUX+ and AUX− are not referenced to COM.
0 = channels are referenced in differential pairs: IN0/IN1, IN2/IN3, IN4/IN5, and IN6/IN7 (see the Channel Sequencer
Details section).
1 = each channel is referenced to a common sense, COM (default).
10 RSV Reserved. Setting or clearing this bit has no effect.
[9:7] PGIA Programmable gain selection (see the Input Structure section). In basic sequencer modes, this register configures
the range for all channels. In advanced sequencer mode, this register sets the range for IN0 (COM = 1) or the IN0/IN1
pair (COM = 0). See the Advanced Mode section for the PGIA configurations of individual channels or channel pairs.
Bit 9 Bit 8 Bit 7 Absolute Input Voltage Range
0 0 0 ±24.576 V
0 0 1 ±10.24 V
0 1 0 ±5.12 V
0 1 1 ±2.56 V
1 0 0 ±1.28 V
1 0 1 ±0.64 V
1 1 0 Not used
1 1 1 ±20.48 V (default)
6 MUX Multiplexer/auxiliary channel input (see the Auxiliary Input Channel section).
0 = selects auxiliary channel on AUX± inputs as active channel.
1 = uses the selected analog front end (AFE) channel/channel pair (default).