Datasheet

Data Sheet ADAS3022
Rev. B | Page 33 of 40
Sampling on the SCK Rising Edge (Alternate Edge)
SPI or other alternate edge transfers typically require more time
to access data because the total data transfer time of these slower
hosts can be >t
DDC
. If this is the case, the time from t
QUIET
to the next
CNV rising edge, which is known as the data access time after
conversion (t
DAC
) and is determined by the user, must be
adjusted by lowering the throughput rate (CNV frequency),
thus providing the necessary time. If this does not allow enough
time, the data access can be broken up so that some data access
occurs during this time followed by the remainder of data
access occurring during the next t
DDC
and t
DDCA
times.
CFG Readback
The CFG result associated with the current conversion can be read
back with an additional 16 SCK burst following the conversion
result (see Figure 69). After the LSB of the conversion result is
clocked out, the MSB of the CFG associated with that conversion
follows. Subsequent SCK falling edges repeat the conversion
result and CFG word. For example, when CPHA is 0, the MSB
of the conversion result is output on the 32
nd
falling edge.
GENERAL CONSIDERATIONS
Because the time to access data is somewhat restricted, the
following guidelines are useful in determining the ADAS3022
throughput, or CNV frequency, and the serial interface details.
Note that in Figure 70 to Figure 72, t
AD
is for reference purposes
only and denotes a time without digital activity because such
activity should not occur prior to or just after sampling.
Data Access During Conversion—Maximum Throughput
The maximum throughput rate per channel is determined
mainly by the maximum SCK period of the host. When using
the maximum throughput rate of 1 MSPS, the ADAS3022 has
an almost symmetric period for both safe data and quiet times
(~500 ns each; see Figure 70). Consequently, t
DDC
is basically
fixed and only provides the host ~500 ns to access data. Note
that in Figure 70, t
AD
is for reference purposes only and denotes
a time without digital activity because such activity should not
occur during the sampling edge. For 17 SCK edges (worst case), the
minimum SCK frequency required to achieve a 1 MSPS (1 µs
between CNV rising) aggregate throughput rate is
MHz34
17
≥
+
≥
DDCAD
tt
SCK
f
Although additional time to access data can be attained by trans-
ferring data during t
DDCA
, this is not recommended because the
ADAS3022 performs sensitive bit decisions during this time. If
t
DDCA
is used, however, the minimum SCK frequency is
MHz25
17
≥
++
≥
DDCADDCAD
tt
t
SCK
f
CS
n
n
nn – 1
n + 2
n + 2 n + 3
n + 1
n + 1
SDO
DIN
SCK
CNV
BUSY
SOC EOC
t
DDC
t
AD
t
DDCA
t
QUIET
10516-026
Figure 70. Data Access During Conversion
Data Access After/Spanning Conversion—Host Determined
Throughput
For hosts that do not have the 34 MHz or 25 MHz SCK rates
available, the maximum throughput rate cannot be achieved
because the data access time after conversion, t
DAC
, must be
increased to allow more time to access data. In this case, there
are three methods to access data:
• The first method is to adjust t
DAC
for 17 SCK edges (worst
case) and the additional
CS
to CNV setup and hold times.
In this case, all data access occurs during t
DAC
. This is the
only method that can be used when using a slow host that
cannot break up data into bytes or other partial data bursts.
• A second method is to break up the data into bursts that
can transfer part of the data during t
DAC
of the current
conversion and the rest of the data during t
DDC
of the next
conversion. Note that
CS
can stay low throughout the CNV
rising phase; however, serial clock activity should pause
while the input is being sampled.
• A third method is to use the second method along with the
additional t
DDCA
, again noting that digital activity must cease
after this time to prevent the current conversion from
becoming corrupted.
In any of these methods, if the time between conversions (t
CYC
)
is exceeded for the fastest possible throughput mode (CMS = 0),
the conversion results will be inaccurate. If this is the case, the
fully asynchronous mode (CMS = 1) must be selected (see the
Conversion Modes section for details).
Figure 71 shows a basic timing diagram for all three methods.
For conversion (n), the data is read back after the end of a
conversion (n), with the remainder of data read into the next
(n + 1) conversion.