Datasheet

Data Sheet ADAS3022
Rev. B | Page 31 of 40
DIGITAL INTERFACE
The ADAS3022 digital interface consists of asynchronous
inputs, a busy indicator, and a 4-wire serial interface for
conversion result readback and configuration register
programming.
This interface uses the three asynchronous signals (CN V,
RESET, and PD) and a 4-wire serial interface composed of
CS
,
SDO, SCK, and DIN.
CS
can also be tied to CNV for some
applications.
Conversion results are available on the serial data output pin
(SDO), and the 16-bit configuration word (CFG) is program-
med on the serial data input pin (DIN). This register controls
settings such as the channel to be converted, the programmable
gain setting, and the reference choice (see the Configuration
Register section for more information).
CONVERSION CONTROL
Conversions are initiated by the CNV input. The ADAS3022 is
fully asynchronous and can perform conversions at any frequency
from dc up to 1 MHz, depending on the conversion mode.
CNV Rising Edge—Start of a Conversion (SOC)
A rising edge on CNV changes the state of the ADAS3022 from
track mode to hold mode and is all that is necessary to initiate a
conversion. All conversion timing clocks are internally generated.
After a conversion is initiated, the ADAS3022 ignores other
activity on the CNV line (governed by the throughput rate) until
the end of the conversion; the conversion can only be aborted
by the power-down (PD) or RESET inputs.
When the ADAS3022 is performing a conversion and the BUSY
output is driven high, the ADAS3022 uses a unique 2-phase
conversion process to allow for safe data access and quiet times.
The CNV signal is decoupled from the
CS
pin, allowing
multiple ADAS3022 devices to be controlled by the same
processor. For applications where SNR is critical, the CNV
source should have very low jitter. This can be achieved by
using a dedicated oscillator or by clocking CNV with a high
frequency, low jitter clock. For applications where jitter is more
tolerable or a single device is in use, CNV can be tied to
CS
. For
more information about sample clock jitter and aperture delay,
refer to the MT-007 Tutorial, Aperture Time, Aperture Jitter,
Aperture Delay Time—Removing the Confusion.
Although CNV is a digital signal, it should be designed to
ensure fast, clean edges with minimal overshoot, undershoot,
and ringing. The CNV trace should be shielded by connecting a
trace to ground, and a low value (such as 50 Ω) serial resistor
termination should be added close to the output of the component
that drives this line. In addition, care should be taken to avoid
digital activity close to the sampling instant because such activity
may result in degraded SNR performance.
BUSY Falling Edge—End of a Conversion (EOC)
The EOC event is indicated by BUSY returning low and can be
used as a host interrupt. In addition, the EOC gates data access
to and from the ADAS3022. If the current conversion result is
not read prior to the following EOC event, the data is lost.
Furthermore, if the CFG update is not completed prior to EOC, it
is discarded and the current configuration is applied to future con-
versions. This pipeline ensures that the ADAS3022 has
sufficient time to acquire the next sample to the specified 16-bit
accuracy.
Conversion Timing
A detailed timing diagram of the conversion process is shown
in Figure 66.
CONVER-
SION
ACQUI-
SITION
CNV
CS
SDO
DIN
BUSY
(n)
SAFE
XXX
XXX
QUIET
DATA
(n – 1)
CFG
(n + 2)
x
x
CFG
(n + 3)
DATA
(n)
x
(n + 1)
(n + 1)
(n)
EOC
(n)
SOC
(n)
t
DDC
t
CH
t
CYC
t
QUIET
t
DAC
t
AD
t
ACQ
t
CCS
t
CBD
t
CONV
t
CCS
t
DDCA
SOC
(n + 1)
10516-022
Figure 66. Basic Conversion Timing
Register Pipeline
To ensure that all CFG updates are applied during a known safe
instant to the various circuit elements, the asynchronous data
transfer is synchronized to the ADAS3022 timing engine using
the EOC event. This synchronization introduces an inherent delay
between updating the CFG register setting and the application
of the configuration to a conversion. This pipeline from the end
of the current conversion (n) consists of a two-deep delay (shown
as (n + 2) in Figure 66) before the CFG setting takes effect. This
means that two SOC and EOC events must elapse before the
setting (that is, new channel, gain, and so on) takes effect. Note
that the nomenclature (n), (n + 1), and so on is used in the
remainder of the following digital sections for simplicity.
There is no pipeline after the end of a conversion, however,
before data can be read back.