Datasheet

Data Sheet ADAS3022
Rev. B | Page 23 of 40
The ADAS3022 offers true high impedance inputs in a differential
structure and rejects common-mode signals present on the inputs.
The ADAS3022 architecture does not require any of the additional
input buffers (op amps) that are usually required to condition
the input signal and drive the ADC inputs when using switched
capacitor-based successive approximation register (SAR) analog-
to-digital converters (ADCs).
The inputs are multiplexed to the PGIA using a high voltage
multiplexer with low charge injection and very low leakage. The
inputs can be configured for a single-ended to common point
(COM) measurement or can be paired for up to four fully
differential inputs with independent gain settings. This requires
using the advanced sequencer or programming sequential
configuration words with the desired gain for each pair. The
digitally controlled, programmable gain is used to select one of
seven voltage input ranges (see Table 7).
When the sequencer option is used, an on-chip sequencer scans
channels in order and offers independent input voltage ranges
for each channel (see the Channel Sequencer Details section).
In this mode, a single configuration word initiates the sequencer
to scan repeatedly without the need to rewrite the register. After
the last channel is scanned, the ADAS3022 automatically begins
at IN0 again and repeats the sequence until a word is written to
stop the sequencer or the asynchronous RESET is asserted.
Additionally, if changes are made to certain configuration bits,
the sequencer is reset to IN0.
The PulSAR-based ADC core is capable of converting 1 MSPS
from a single rising edge on the convert start input (CNV). The
conversion results are available in twos complement format and
are presented on the serial data output (SDO). The digital interface
uses a dedicated chip select pin (
CS
) to transfer data to and from
the ADAS3022 and also provides a BUSY indicator, asynchronous
RESET, and power-down (PD) inputs.
The ADAS3022 on-chip reference uses an internal temperature
compensated 2.5 V output band gap reference and a precision
buffer amplifier to provide the 4.096 V high precision system
reference.
All of the bits in Table 11 are configured through a serial (SPI-
compatible), 16-bit configuration register (CFG). Configuration
and conversion results can be read after or during a conversion,
or the readback option can be disabled.
The ADAS3022 requires a minimum of three power supplies: +5 V,
+15 V, and −15 V. On-chip low dropout regulators provide the
necessary 2.5 V system voltages and must be decoupled externally
via dedicated pins (ACAP, DCAP, and RCAP). The ADAS3022
can be interfaced to any 1.8 V to 5 V digital logic family using
the dedicated VIO logic level voltage supply (see Table 9).
A rising edge on CNV initiates a conversion and changes the
state of the ADAS3022 from track to hold. In this state, the
ADAS3022 performs analog signal conditioning. When the
signal conditioning is complete, the ADAS3022 returns to the
track state while at the same time quantizing the sample. This
two-part process satisfies the necessary settling time requirement
while achieving a fast throughput rate of up to 1 MSPS with 16-bit
accuracy.
PHASE
CNV
HOLD CONVERT/TRACK
t
CYC
t
ACQ
10516-006
Figure 52. ADAS3022 System Timing
Regardless of the type of signal (differential or single-ended,
antiphase or nonantiphase, symmetric or asymmetric), the
ADAS3022 converts all signals present on the enabled inputs in
a differential fashion, like an industry-standard difference or
instrumentation amplifier.
The conversion result is available after the conversion is complete
and can be read back at any time before the end of the next
conversion. Reading back data should be avoided during the
quiet period, as indicated by BUSY being active high. Because
the ADAS3022 has an on-board conversion clock, the serial
clock (SCK) is not required for the conversion process. It is only
required to present results to the user.
TRANSFER FUNCTION
The ideal transfer characteristics of the ADAS3022 are shown in
Figure 53. With the inputs configured for differential input
ranges, the data output is twos complement, as described in
Table 6.
100 ... 000
100 ... 001
100 ... 010
011 ... 101
011 ... 110
011 ... 111
TWOS
COMPLEMENT
ADC CODE
ANALOG INPUT
+FSR – 1.5LSB
+FSR – 1LSB
–FSR + 1LSB
–FSR
–FSR + 0.5LSB
10516-007
Figure 53. ADC Ideal Transfer Function