Datasheet

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Rev. A | Page 55 of 80
CONTROL REGISTERS DETAILS
For each register address, the default setting is noted in a default column in addition to being noted in the function column by “(default)”;
this format applies throughout the register map.
Table 25. Serial Bit Assignment
B31 [B30:B24] [B23:B0]
R
/W
Address bits
Data bits (MSB first)
Table 26. ECG Control Register (ECGCTL) Address 0x01, Reset Value = 0x000000
R/W
Default Bit Name Function
R/W 0 23 LAEN ECG channel enable; shuts down power to the channel; the input becomes high-Z.
0 (default) = disables ECG channel. When disabled, the entire ECG channel is shut down and
dissipating minimal power.
1 = enables ECG channel.
R/W 0 22 LLEN
R/W 0 21 RAEN
R/W 0 20 V1EN
R/W 0 19 V2EN
R 0 [18:11] Reserved Reserved, set to 0.
R/W 0 10 CHCONFIG
Setting this bit selects the differential analog front end (AFE) input. See
Figure 57.
0 (default) = single-ended input (digital lead mode or electrode mode).
1 = differential input (analog lead mode).
R/W 00 [9:8] GAIN [1:0]
Preamplifier and anti-aliasing filter overall gain.
00 (default) = GAIN 0 = ×1.4.
01 = GAIN 1 = ×2.1.
10 = GAIN 2 = ×2.8.
11 = GAIN 3 = ×4.2 (user gain calibration is required for this gain setting).
R/W 0 7 VREFBUF VREF buffer enable.
0 (default) = disabled.
1 = enabled (when using the internal VREF, VREFBUF must be enabled).
R/W 0 6 CLKEXT Use external clock instead of crystal oscillator. The crystal oscillator is automatically disabled if
configured as a slave in gang mode and the slave device should receive the clock from the master
device.
0 (default) = XTAL is clock source.
1 = CLK_IO is clock source.
R/W 0 5 Master In gang mode, this bit selects the master (SYNC_GANG pin is configured as an output). When in single
channel mode (gang = 0), this bit is ignored
. ADAS1000-2 cannot be configured as a master device.
0 (default) = slave.
1 = master.
R/W 0 4 Gang Enable gang mode. Setting this bit causes CLK_IO and SYNC_GANG to be activated.
0 (default) = single channel mode.
1 = gang mode.
R/W 0 3 HP Selects the noise/power performance. This bit controls the ADC sampling frequency. See the
Specifications section for further details.
0 (default) = 1 MSPS, low power.
1 = 2 MSPS, high performance/low noise.
R/W 0 2 CNVEN Conversion enable. Setting this bit enables the ADC conversion and filters.
0 (default) = idle.
1 = conversion enable.
R/W 0 1 PWREN Power enable. Clearing this bit powers down the device. All analog blocks are powered down and the
external crystal is disabled. The register contents are retained during power down as long as DVDD is
not removed.
0 (default) = power down.
1 = power enable.
R/W 0 0 SWRST Software reset. Setting this bit clears all registers to their reset value. This bit automatically clears itself.
The software reset requires a NOP command to complete the reset.
0 (default) = NOP.
1 = reset.