Datasheet

ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Rev. A | Page 54 of 80
SPI REGISTER DEFINITIONS AND MEMORY MAP
In 2 kHz and 16 kHz data rates, data takes the form of 32-bit words. Bit A6 to Bit A0 serve as word identifiers. Each 32-bit word has 24
bits of data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data).
Table 24. SPI Register Memory Map
R
/W12
1
A[6:0] D[23:0] Register Name Table Register Description Reset Value
R 0x00 XXXXXX NOP NOP (no operation) 0x000000
R/W 0x01 dddddd ECGCTL Table 26 ECG control 0x000000
R/W 0x02 dddddd LOFFCTL Table 27 Lead-off control 0x000000
R/W 0x03 dddddd RESPCTL Table 28 Respiration control
2
0x000000
R/W 0x04 dddddd PACECTL Table 29 Pace detection control 0x000F88
R/W 0x05 dddddd CMREFCTL Table 30 Common-mode, reference, and shield drive control 0xE00000
R/W 0x06 dddddd GPIOCTL Table 31 GPIO control 0x000000
R/W 0x07 dddddd PACEAMPTH Table 32
Pace amplitude threshold
2
0x242424
R/W 0x08 dddddd TESTTONE Table 33 Test tone 0x000000
R/W 0x09 dddddd CALDAC Table 34 Calibration DAC 0x002000
R/W 0x0A dddddd FRMCTL Table 35 Frame control 0x079000
R/W 0x0B dddddd FILTCTL Table 36 Filter control 0x000000
R/W 0x0C dddddd LOFFUTH Table 37 AC lead-off upper threshold 0x00FFFF
R/W 0x0D dddddd LOFFLTH Table 38 AC lead-off lower threshold 0x000000
R/W 0x0E dddddd PACEEDGETH Table 39
Pace edge threshold
2
0x000000
R/W 0x0F dddddd PACELVLTH Table 40
Pace level threshold
2
0x000000
R 0x11 XXXXXX LADATA Table 41 LA or Lead I data 0x000000
R 0x12 XXXXXX LLDATA Table 41 LL or Lead II data 0x000000
R 0x13 XXXXXX RADATA Table 41 RA or Lead III data 0x000000
R 0x14 XXXXXX V1DATA Table 41 V1 or V1’ data 0x000000
R 0x15 XXXXXX V2DATA Table 41 V2 or V2’ data 0x000000
R 0x1A XXXXXX PACEDATA Table 42
Read pace detection data/status
2
0x000000
R 0x1B XXXXXX RESPMAG Table 43
Read respiration data—magnitude
2
0x000000
R 0x1C XXXXXX RESPPH Table 44
Read respiration data—phase
2
0x000000
R 0x1D XXXXXX LOFF Table 45 Lead-off status 0x000000
R 0x1E XXXXXX DCLEAD-OFF Table 46 DC lead-off 0x000000
R 0x1F XXXXXX OPSTAT Table 47 Operating state 0x000000
R/W 0x20 dddddd EXTENDSW Table 48 Extended switch for respiration inputs 0x000000
R/W 0x21 dddddd CALLA Table 49 User gain calibration LA 0x000000
R/W 0x22 dddddd CALLL Table 49 User gain calibration LL 0x000000
R/W 0x23 dddddd CALRA Table 49 User gain calibration RA 0x000000
R/W 0x24 dddddd CALV1 Table 49 User gain calibration V1 0x000000
R/W 0x25 dddddd CALV2 Table 49 User gain calibration V2 0x000000
R 0x31 dddddd LOAMLA Table 50 Lead-off amplitude for LA 0x000000
R 0x32 dddddd LOAMLL Table 50 Lead-off amplitude for LL 0x000000
R 0x33 dddddd LOAMRA Table 50 Lead-off amplitude for RA 0x000000
R 0x34 dddddd LOAMV1 Table 50 Lead-off amplitude for V1 0x000000
R 0x35 dddddd LOAMV2 Table 50 Lead-off amplitude for V2 0x000000
R 0x3A dddddd PACE1DATA Table 51
Pace1 width and amplitude
2
0x000000
R 0x3B dddddd PACE2DATA Table 51
Pace2 width and amplitude
2
0x000000
R 0x3C dddddd PACE3DATA Table 51
Pace3 width and amplitude
2
0x000000
R 0x40 dddddd FRAMES Table 52 Frame header 0x800000
R 0x41 XXXXXX CRC Table 53 Frame CRC 0xFFFFFF
x Other XXXXXX Reserved1
3
Reserved XXXXXX
1
R/W = register both readable and writable; R = read only.
2
ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features.
3
Reserved bits in any register are undefined. In some cases a physical (but unused) memory bit may be present—in other cases not. Do not issue commands to
reserved registers/space. Read operations of unassigned bits are undefined.