Datasheet

ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Rev. A | Page 50 of 80
Internal operations are synchronized to the internal master
clock at either 2.048 MHz or 1.024 MHz (ECGCTL[3]: HP = 1
and HP = 0, respectively, see Table 26). Because there is no
guaranteed relationship between the internal clock and the SPI's
SCLK signal, an internal handshaking scheme is used to ensure
safe data transfer between the two clock domains. A full
handshake requires three internal clock cycles and imposes an
upper speed limit on the SCLK frequency when reading frames
with small word counts. This is true for all data frame rates.
SCLK (max) = (1.024 MHz × (1 + HP) × words_per_frame ×
bits_per_word)/3; or 40 MHz, whichever is lower.
Exceeding the maximum SCLK frequency for a particular
operating mode causes erratic behavior in the
DRDY
signal
and results in the loss of data.
Data Rate and Skip Mode
Although the standard frame rates available are 2 kHz, 16 kHz,
and 128 kHz, there is also a provision to skip frames to further
reduce the data rate. This can be configured in the frame
control register (see Table 35).
Data Ready (
DRDY
)
The
DRDY
pin is used to indicate that a frame composed of
decimated data at the selected data rate is available to read. It
is high when busy and low when ready. Send commands only
when the status of
DRDY
is low or ready. During power-on, the
status of
DRDY
is high (busy) while the device initializes itself.
When initialization is complete,
DRDY
goes low and the user
can start configuring the device for operation. When the device
is configured and enabled for conversions by writing to the
conversion bit (CNVEN) in the ECGCTL register, the ADCs
start to convert and the digital interface starts to make data
available, loading them into the buffer when ready. If
conversions are enabled and the buffer is empty, the device is
not ready and
DRDY
goes high. Once the buffer is full,
DRDY
goes low to indicate that data is ready to be read out of the
device. If the device is not enabled for conversions, the
DRDY
ignores the state of the buffer full status.
When reading packets of data, the entire data packet must be
read; otherwise,
DRDY
stays low.
There are three methods of detecting
DRDY
status.
•
DRDY
pin. This is an output pin from the ADAS1000/
ADAS1000-1/ADAS1000-2 that indicates the device read
or busy status. No data is valid while this pin is high.
The
DRDY
signals that data is ready to be read by driving
low and remaining low until the entire frame has been
read. It is cleared when the last bit of the last word in the
frame is clocked onto SDO. The use of this pin is optional.
• SDO pin. The user can monitor the voltage level of the
SDO pin by bringing
CS
low. If SDO is low, data is ready;
if high, busy. This does not require clocking the SCLK
input. (CPHA = CPOL = 1 only).
• One of the first bits of valid data in the header word
available on SDO is a data ready status bit (see Table 41).
Within the configuration of the ADAS1000/ADAS1000-1/
ADAS1000-2, the user can set the header to repeat until
the data is ready. See Bit 6 (RDYRPT) in the frame control
register in Table 35.
Detecting Missed Conversion Data
To ensure that the current data is valid, the entire frame must
be read at the selected data rate. If a read of the entire frame
takes longer than the selected data rate allows, the internal
buffer is not loaded with the latest conversion data. The frame
header register (see Table 52) provides four settings to indicate
an overflow of frame data. The settings of Bits[29:28] report
how many frames have been missed since the last valid frame
read. A missed frame may occur as a result of the last read
taking too long. The data in the current frame is valid data, but
it is not the current data. It is the calculation made directly after
the last valid read.
To clear such an overflow, the user must read the entire frame.