Datasheet

Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2
Rev. A | Page 49 of 80
In the 128 kHz data rate, all write words are still 32-bit writes
but the read words in the data packet are now 16 bits (upper
16 bits of register). There are no address bits, only data bits.
Register space that is larger than 16 bits spans across 2 ×
16-bit words (for example, pace and respiration).
Data Frames/Packets
The general data packet structure is shown in Table 18. Data
can be received in two different frame formats. For the 2 kHz
and 16 kHz data rates, a 32-bit data format is used (where the
register address is encapsulated in the upper byte, identifying
the word within the frame) (see Table 20). For the 128 kHz data
rate, words are provided in 16-bit data format (see Table 21).
When the configuration is complete, the user can begin reading
frames by issuing a read command to the frame header register
(see Table 52). The ADAS1000/ADAS1000-1/ADAS1000-2
continue to make frames available until another register address
is written (read or write command). To continue reading frame
data, continue to write all zeros on SDI, which is a write of the
NOP register (Address 0x00). A frame is interrupted only when
another read or write command is issued.
Each frame can be a large amount of data plus status words.
CS
can toggle between each word of data within a frame, or it can
be held constantly low during the entire frame.
By default, a frame contains 11 × 32 bit words when reading at
2 kHz or 16 kHz data rates; similarly, a frame contains 13 × 16-
bit words when reading at 128 kHz. The default frame
configuration does not include the optional respiration phase
word; however, this word can be included as needed.
Additionally any words not required can be excluded from the
frame. To arrange the frame with the words of interest,
configure the appropriate bits in the frame control register (see
Table 35). The complete set of words per frame are 12 × 32-bit
words for the 2 kHz or 16 kHz data rates, or 15 × 16-bit words
at 128 kHz.
Any data not available within the frame can be read between
frames. Reading a register interrupts the frame and requires the
user to issue a new read command of Address 0x40 (see
Table 52) to start framing again.
Read Mode
Although the primary reading function within the ADAS1000/
ADAS1000-1/ADAS1000-2 is the output of the ECG frame
data, the devices also allow reading of all configuration regis-
ters. To read a register, the user must first address the device
with a read command containing the particular register address.
If the device is already in data framing mode, the read register
command can be interleaved between the frames by issuing a
read register command during the last word of frame data.
Data shifted out during the next word is the register read data.
To return to framing mode, the user must re-enable framing
by issuing a read of the frame header register (Address 0x40)
(see Table 52). This register write can be used to flush out the
register contents from the previous read command.
Table 18. Example of Reading Registers and Frames
SDI
….. NOP
Read
Address
N
Read
frames
NOP NOP …..
SDO
…..
Frame
data
Frame
CRC
Register
Data N
Frame
header
Frame
data
…..
Regular register reads are always 32 bits long and MSB first.
Serial Clock Rate
The SCLK can be up to 40 MHz, depending on the IOVDD
voltage level as shown in Table 5. The minimum SCLK
frequency is set by the requirement that all frame data be
clocked out before the next frame becomes available.
SCLK (min) = frame_rate × words_per_frame × bits_per_word
The minimum SCLK for the various frame rates is shown in
Table 19.
Table 19. SCLK Clock Frequency vs. Packet Data/Frame Rates
Frame
Rate
Word
Size
Maximum
Words/Frame
1
Minimum
SCLK
128 kHz 16 bits 15 words 30.72 MHz
16 kHz 32 bits 12 words 6.14 MHz
2 kHz 32 bits 12 words 768 kHz
1
This is the full set of words that a frame contains. It is programmable and can
be configured to provide only the words of interest. See Table 35.
Table 20. Default 2 kHz and 16 kHz Data Rate: 32-Bit Frame Word Format
Register
Header Lead I/LA Lead II/LL Lead III/RA V1’/V1 V2’/V2 PACE RESPM RESPPH LOFF GPIO CRC
Address
0x40
0x11
0x12
0x13
0x14
0x15
0x1A
0x1B
0x1C
0x1D
0x06
0x41
Table 21. Default 128 kHz Data Rate: 16-Bit Frame Word Format
1
Register
Header
Lead I/LA
Lead II/LL
Lead III/RA
V1’/V1
V2’/V2
PACE1 PACE2 RESPM1 RESPM2 LOFF GPIO CRC
Address
0x40 0x11 0x12 0x13 0x14 0x15
0x1A 0x1B
0x1D 0x06 0x41
1
Respiration phase words (2x 16-bit words) are not shown in this frame, but could be included.