Datasheet

ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Rev. A | Page 40 of 80
PACING ARTIFACT DETECTION FUNCTION
(ADAS1000 ONLY)
The pacing artifact validation function qualifies potential
pacing artifacts and measures the width and amplitude of valid
pulses. These parameters are stored in and available from any of
the pace dataregisters (Address 0x1A, Address 0x3A to Address
0x3C). This function runs in parallel with the ECG channels.
Digital detection is performed using a state machine operating
on the 128 kHz 16-bit data from the ECG decimation chain.
The main ECG signals are further decimated before appearing
in the 2 kHz output stream so that detected pace signals are not
perfectly time-aligned with fully-filtered ECG data. This time
difference is deterministic and may be compensated for.
The pacing artifact validation function can detect and
measure pacing artifacts with widths from 100 μs to 2 ms
and with amplitudes of <400 μV to >1000 m V. Its filters are
designed to reject heartbeat, noise, and minute ventilation
pulses. The flowchart for the pace detection algorithm is
shown in Figure 70.
The ADAS1000 pace algorithm can operate with the ac lead-off
and respiration impedance measurement circuitry enabled.
Once a valid pace has been detected in the assigned leads, the
pace-detected flags appear in the header word (see Table 52) at
the start of the packet of ECG words. These bits indicate that a
pace was qualified. Further information on height and width of
pace is available by reading the contents of Address 0x1A (Register
PACEDATA, see Table 42). This word can be included in the
ECG data packet/frame as dictated by the frame control register
(see Table 35). The data available in the PACEDATA register
is limited to seven bits total for width and height information;
therefore, if more resolution is required on the pace height
and width, this is available by issuing read commands of the
PACExDATA registers (Address 0x3A to Address 0x3C) as
shown in Table 51.
Some users may not wish to use three pace leads for detection.
In this case, Lead II would be the vector of choice
because this lead is likely to display the best pacing artifact. The
other two pace instances can be disabled if not in use.
The on-chip filtering contributes some delay to the pace signal
(see the Pace Latency section).
Choice of Leads
Three identical state machines are available and can be
configured to run on up to three of four possible leads (Lead I,
Lead II, Lead III, and aVF) for pacing artifact detection. All
necessary lead calculations are performed internally and are
independent of EGG channel settings for output data rate, low-
pass filter cutoff, and mode (electrode, analog lead, common
electrode). These calculations take into account the available
front-end configurations as detailed in Table 13.
The pace detection algorithm searches for pulses by analyzing
samples in the 128 kHz ECG data stream. The algorithm
searches for an edge, a peak, and a falling edge as defined by
values in the PACEEDGETH, PACEAMPTH, and PACELVLTH
registers, along with fixed width qualifiers. The post-reset
default register values can be overwritten via the SPI bus, and
different values can be used for each of the three pace detection
state machines.
The first step in pace detection is to search the data stream for
a valid leading edge. Once a candidate edge has been detected,
the algorithm begins searching for a second, opposite-polarity
edge that meets with pulse width criteria and passes the
(optional) noise filters. Only those pulses meeting all the
criteria are flagged as valid pace pulses. Detection of a
valid pace pulse sets the flag(s) in the frame header register
and stores amplitude and width information in the PACEDATA
register (Address 0x1A; see Table 42). The pace algorithm looks
for a negative or positive pulse.
Table 13. Pace Lead Calculation
0x01 [10]
1
0x05 [8]
2
Configuration
0x04 [8:3]
3
00 01 10 11
Lead I
(LA − RA)
Lead II
(LL − RA)
Lead III
(LL − LA)
aVF
(Lead II + Lead III)/2
0 0 Digital leads LA − RA
CH1 − CH3
LL − RA
CH2 − CH3
LL − LA
CH2 − CH1
LL − (LA + RA)/2
CH2 − (CH1 + CH3)/2
0 1 Common
electrode leads
Lead I
CH1
Lead II
CH2
Lead II – Lead I
CH2 − CH1
lead II − 0.5 × Lead I
CH2 − 0.5 × CH1
1 X Analog leads Lead I
CH1
Lead II
−CH3
Lead III
CH2
Lead II − 0.5 × Lead I − CH3 − 0.5 × CH1
1
Register ECGCTL, Bit CHCONFIG, see Table 26.
2
Register CMREFCTL, Bit CEREFEN, see Table 30.
3
Register PACECTL, Bit PACExSEL [1:0], see Table 29.