Datasheet
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Rev. A | Page 16 of 80
ADAS1000 ADAS1000-1 ADAS1000-2
Mnemonic Description
LQFP LFCSP LFCSP LQFP LFCSP
14 2 2 ECG5_V2 Analog Input, Chest Electrode 2 or Auxiliary Biopotential Input (V2).
10 6 ECG1 Analog Input 1.
11 5 ECG2 Analog Input 2.
12 4 ECG3 Analog Input 3.
13
3
ECG4
Analog Input 4.
14 2 ECG5 Analog Input 5.
4 12 EXT_RESP_RA Optional External Respiration Input.
5 11 EXT_RESP_LL Optional External Respiration Input.
6 10 EXT_RESP_LA Optional External Respiration Input.
62 16 RESPDAC_LL
Optional path for higher performance respiration resolution, respiration
DAC drive, Negative Side 0.
60 18
SHIELD/
RESPDAC_LA
Shared Pin (User-Configured).
Output of Shield Driver (SHIELD).
Optional Path for Higher Performance Respiration Resolution, Respiration
DAC Drive, Negative Side 1 (RESPDAC_LA).
3 13 RESPDAC_RA
Optional Path for Higher Performance Respiration Resolution, Respiration
DAC Drive, Positive Side.
22 52 52 CM_OUT/WCT
Common-Mode Output Voltage (Average of Selected Electrodes). Not
intended to drive current.
19 55 55 19 55 CM_IN Common-Mode Input.
21 53 53 21 53 RLD_SJ Summing Junction for Right Leg Drive Amplifier.
20 54 54 RLD_OUT Output and Feedback Junction for Right Leg Drive Amplifier.
61 17 17 CAL_DAC_IO
Calibration DAC Input/Output. Output for a master device, input for a
slave. Not intended to drive current.
9 7 7 9 7 REFIN
Reference Input. For standalone mode, use REFOUT connected to REFIN.
External 10 μF with ESR < 0.2 Ω in parallel with 0.1 μF bypass capacitors to
GND are required and should be placed as close to the pin as possible. An
external reference can be connected to REFIN.
8 8 8 8 8 REFOUT Reference Output.
7 9 9 7 9 REFGND Reference Ground. Connect to a clean ground.
27, 28 47, 46 47, 46 XTAL1, XTAL2
External crystal connects between these two pins; external clock drive
should be applied to CLK_IO. Each XTAL pin requires 15 pF to ground.
29 45 45 CLK_IO
Buffered Clock Input/Output. Output for a master device; input for a slave.
Powers up in high impedance.
41 35 35 41 35
CS
Chip Select and Frame Sync, Active Low.
CS
can be used to frame each
word or to frame the entire suite of data in framing mode.
44 32 32 44 32 SCLK
Clock Input. Data is clocked into the shift register on a rising edge and
clocked out on a falling edge.
43 33 33 43 33 SDI Serial Data Input.
53 25 25 53 25
PD
Power-Down, Active Low.
45 31 31 45 31 SDO
Serial Data Output. This pin is used for reading back register configuration
data and for the data frames.
42 34 34 42 34
DRDY
Digital Output. This pin indicates that conversion data is ready to be read
back when low, busy when high. When reading packet data, the entire
packet must be read to allow
DRDY
to return high.
54
24
24
54
24
RESET
Digital Input. This pin has an internal pull-up. This pin resets all internal
nodes to their power-on reset values.
52 26 26 52 26 SYNC_GANG
Digital Input/Output (Output on Master, Input on Slave). Used for
synchronization control where multiple devices are connected together.
Powers up in high impedance.
36 40 40
GPIO0/
MCS
General-Purpose I/O or Master 128 kHz SPI
CS
.
37 39 39 GPIO1/MSCLK General-Purpose I/O or Master 128 kHz SPI SCLK.
38 38 38 GPIO2/MSDO General-Purpose I/O or Master 128 kHz SPI SDO.
39 37 37 GPIO3 General-Purpose I/O.