Datasheet

ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet
Rev. A | Page 12 of 80
Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000/ ADAS1000-1 Only
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. T
A
= −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at T
A
= 25°C. The following timing
specifications apply for the master interface when ECGCTL register is configured for high performance mode (ECGCTL[3] = 1), see
Table 26.
Table 6.
Parameter
1
Min Typ Max Unit Description
Output Frame Rate
2
128 kHz All five 16-bit ECG data-words are available at frame rate of 128 kHz only
f
SCLK
2
2.5 × crystal
frequency
MHz Crystal frequency = 8.192 MHz
t
MCSSA
24.4 ns
MCS
valid setup time
t
MDO
0
ns
MSCLK rising edge to MSDO valid delay
t
MCSHD
48.8 ns
MCS
valid hold time from MSCLK falling edge
t
MCSW
2173 ns
MCS
high time, SPIFW = 0,
MCS
asserted for entire frame as shown in
Figure 5, and configured in Table 31
2026 ns
MCS
high time, SPIFW = 1,
MCS
asserted for each word in frame as shown in
Figure 6 and configured in Table 31
1
Guaranteed by characterization, not production tested.
2
Guaranteed by design, not production tested.
Figure 5. Data Read and Write Timing Diagram for SPIFW = 0, Showing Entire Packet Of Data (Header, 5 ECG Words, and CRC Word)
Figure 6. Data Read and Write Timing Diagram for SPIFW = 1, Showing Entire Packet Of Data (Header, 5 ECG Words, and CRC Word)
t
MSCLK
t
MCSSA
09660-105
t
MSCLK
2
MSCLK
MCS
t
MCSHD
MSDO
D0_15
t
MDO
MSB
D0_14 D0_1
D1_15
LSB
SPIFW = 0*
D5_0
D0_0
D1_14
*SPIFW = 0 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1/2 MSCLK CYCLE BETWEEN EACH WORD.
D6_15
MSB
D6_14
MSB LSB
D6_0
LSB
HEADER: 0xF AND 12-BIT COUNTER
5 × 16-BIT ECG DATA
16-BIT CRC WORD
t
MCSW
t
MSCLK
t
MCSSA
t
MCSHD
MSCLK
MCS
MSDO
SPIFW = 1*
t
MSCLK
t
MCSW
D0_15
t
MDO
MSB
D0_14 D0_1
D1_15
LSB
D5_0
D0_0
D1_14
D6_15
MSB
D6_14
MSB LSB
D6_0
LSB
5 × 16-BIT ECG DATAHEADER: 0xF AND 12-BIT COUNTER 16-BIT CRC WORD
09660-005
*SPIFW = 1 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1 MSCLK CYCLE BETWEEN EACH WORD.