Datasheet

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Low Power, Five Electrode

Electrocardiogram (ECG) Analog Front End

Data Sheet

ADAS1000/ADAS1000-1/ADAS1000-2

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FEATURES

Biopotential signals in; digitized signals out

5 acquisition (ECG) channels and one driven lead

Parallel ICs for up to 10+ electrode measurements

Master ADAS1000 or ADAS1000-1 used with Slave

ADAS1000-2

AC and DC lead-off detection

Internal pace detection algorithm on 3 leads

Support for user’s own pace

Thoracic impedance measurement (internal/external path)

Selectable reference lead

Scalable noise vs. power control, power-down modes

Low power operation from

11 mW (1 lead), 15 mW (3 leads), 21 mW (all electrodes)

Lead or electrode data available

Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38

R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005,

IEC60601-2-25 ed. 2.0 :2011, IEC60601-2-27 ed. 2.0

b:2005, IEC60601-2-51 ed. 1.0 b: 2005

Fast overload recovery

Low or high speed data output rates

Serial interface SPI-/QSPI™-/DSP-compatible

56-lead LFCSP package (9 mm × 9 mm)

64-lead LQFP package (10 mm × 10 mm body size)

APPLICATIONS

ECG: monitor and diagnostic

Bedside patient monitoring, portable telemetry, Holter,

AED, cardiac defibrillators, ambulatory monitors, pace

maker programmer, patient transport, stress testing

GENERAL DESCRIPTION

The ADAS1000/ADAS1000-1/ADAS1000-2 measure electro

cardiac (ECG) signals, thoracic impedance, pacing artifacts,

and lead-on/off status and output this information in the form

of a data frame supplying either lead/vector or electrode data at

programmable data rates. Its low power and small size make it

suitable for portable, battery-powered applications. The high

performance also makes it suitable for higher end diagnostic

machines.

The ADAS1000 is a full-featured, 5-channel ECG including

respiration and pace detection, while the ADAS1000-1 offers

only ECG channels with no respiration or pace features.

Similarly, the ADAS1000-2 is a subset of the main device and

is configured for gang purposes with only the ECG channels

enabled (no respiration, pace, or right leg drive).

The ADAS1000/ADAS1000-1/ADAS1000-2 are designed to

simplify the task of acquiring and ensuring quality ECG signals.

They provide a low power, small data acquisition system for

biopotential applications. Auxiliary features that aid in better

quality ECG signal acquisition include: multichannel averaged

driven lead, selectable reference drive, fast overload recovery,

flexible respiration circuitry returning magnitude and phase

information, internal pace detection algorithm operating on

three leads, and the option of ac or dc lead-off detection.

Several digital output options ensure flexibility when

monitoring and analyzing signals. Value-added cardiac post

processing is executed externally on a DSP, microprocessor, or

FPGA.

Because E

CG systems span different applications, the

ADAS1000/ADAS1000-1/ADAS1000-2 feature a power/

noise scaling architecture where the noise can be reduced

at the expense of increasing power consumption. Signal

acquisition channels may be shut down to save power. Data

rates can be reduced to save power.

To ease manufacturing tests and development as well as offer

holistic power-up testing, the ADAS1000/ADAS1000-1/

ADAS1000-2 offer a suite of features, such as dc and ac test

excitation via the calibration DAC and CRC redundancy testing

in addition to readback of all relevant register address space.

The input structure is a differential amplifier input thereby

allowing users a variety of configuration options to best suit

their application.

The ADAS1000/ADAS1000-1/ADAS1000-2 are available in

two package options: either a 56-lead LFCSP or a 64-lead

LQFP package; they are specified over −40°C to +85°C

temperature range.

Summary of content (80 pages)

PAGE 1
Data Sheet Low Power, Five Electrode Electrocardiogram (ECG) Analog Front End ADAS1000/ADAS1000-1/ADAS1000-2 FEATURES Biopotential signals in; digitized signals out 5 acquisition (ECG) channels and one driven lead Parallel ICs for up to 10+ electrode measurements Master ADAS1000 or ADAS1000-1 used with Slave ADAS1000-2 AC and DC lead-off detection Internal pace detection algorithm on 3 leads Support for user’s own pace Thoracic impedance measurement (internal/external path) Selectable reference lead Scala
PAGE 2
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Extend Switch On Respiration Paths ....................................... 39 Applications ....................................................................................... 1 Pacing Artifact Detection Function (ADAS1000 Only) ....... 40 General Description .........................................................................
PAGE 3
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 FUNCTIONAL BLOCK DIAGRAM REFIN REFOUT CAL_DAC_IO RLD_OUT CM_IN RLD_SJ CM_OUT/WCT DRIVEN LEAD AMP – VREF CALIBRATION DAC SHIELD SHIELD DRIVE AMP + AVDD IOVDD ADCVDD ADCVDD, DVDD 1.8V REGULATORS DVDD VCM_REF (1.
PAGE 4
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet SPECIFICATIONS AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. Decoupling for reference and supplies as noted in the Power Supply, Grounding, and Decoupling Strategy section. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. For specified performance, internal ADCVDD and DVDD linear regulators have been used.
PAGE 5
Data Sheet Parameter Gain Error Gain Matching ADAS1000/ADAS1000-1/ADAS1000-2 Min −1 Typ +0.01 Max +1 Unit % −2 −0.1 −0.5 +0.1 +0.02 +0.1 25 +2 +0.1 +0.
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ADAS1000/ADAS1000-1/ADAS1000-2 Parameter RIGHT LEG DRIVE/DRIVEN LEAD (ADAS1000/ADAS1000-1 ONLY) Output Voltage Range RLD_OUT Short Circuit Current Closed-Loop Gain Range2 Slew Rate2 Input Referred Noise1 Amplifier GBP2 DC LEAD-OFF Data Sheet Min Typ Max Unit 0.2 −5 ±2 AVDD − 0.2 +5 V mA 25 V/V mV/ms μV p-p MHz 200 8 1.5 Lead-Off Current Accuracy High Threshold Level1 ±10 2.4 % V Low Threshold Level1 Threshold Accuracy AC LEAD-OFF 0.
PAGE 7
Data Sheet Parameter CLOCK_IO Operating Frequency2 Input Duty Cycle2 Output Duty Cycle2 DIGITAL INPUTS Input Low Voltage, VIL Input High Voltage, VIH Input Current, IIH, IIL Pin Capacitance2 DIGITAL OUTPUTS Output Low Voltage, VOL Output High Voltage, VOH Output Rise/Fall Time DVDD REGULATOR Output Voltage Available Current1 Short Circuit Current limit ADCVDD REGULATOR Output Voltage Short Circuit Current Limit POWER SUPPLY RANGES2 AVDD IOVDD ADCVDD DVDD POWER SUPPLY CURRENTS AVDD Standby Current IOVDD Stan
PAGE 8
ADAS1000/ADAS1000-1/ADAS1000-2 Parameter OTHER FUNCTIONS 4 Power Dissipation Respiration Shield Driver Min Typ 7.6 150 Data Sheet Max Unit Test Conditions/Comments mW μW Guaranteed by characterization, not production tested. Guaranteed by design, not production tested. 3 ADCVDD and DVDD can be powered from an internal LDO or, alternatively, can be powered from external 1.8 V rail, which may result in a lower power solution. 4 Pace is a digital function and incurs no power penalty. 1 2 Rev.
PAGE 9
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 NOISE PERFORMANCE Table 3. Typical Input Referred Noise over 0.5 Second Window (µV p-p) 1 Mode Analog Lead Mode 3 High Performance Mode Data Rate 2 GAIN 0 (×1.4) ±1 VCM GAIN 1 (×2.1) ±0.67 VCM GAIN 2 (×2.8) ±0.5 VCM GAIN 3 (×4.2) ±0.3 VCM 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 8 14 6 11 5 9 4 7.5 Typical values measured at 25°C, not subject to production test. Data gathered using the 2 kHz packet/frame rate is measured over 0.5 seconds.
PAGE 10
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet TIMING CHARACTERISTICS Standard Serial Interface AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. Table 5. Parameter 1 Output Rate 2 3.3 V 2 SCLK Cycle Time tCSSA tCSHA tCH tCL tDO tDS tDH tCSSD tCSHD tCSW 25 8.5 3 8 8 8.5 11 2 2 2 2 25 tDRDY_CS2 tCSO RESET Low Time2 0 6 20 2 1.
PAGE 11
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 tDRDY_CS DRDY tCH SCLK tCL tCSSA tCSSD tCSHD tCSHA CS tDS tCSW tDH MSB SDI LSB DB[29] N DB[25] N DB[24] N DB[31] N DB[30] N R/W ADDRESS = 0x40 (FRAMES) DB[23] DB[1] LSB MSB DB[0] N DB[1] N+1 DB[30] N+1 DB[31] N+1 DB[0] N+1 DATA = NOP or 0x40 DATA MSB SDO DRDY DB[30] N–1 DB[24] DB[23] N–1 N–1 DB[25] N–1 DB[1] N–1 LSB MSB LSB DB[31] N–1 DB[0] N–1 DB[31] N tDO PREVIOUS DATA DB[30] N DB[1] N DB[0] N HEADER (FIRST WORD OF FRAM
PAGE 12
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000/ ADAS1000-1 Only AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C.
PAGE 13
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter AVDD to AGND IOVDD to DGND ADCVDD to AGND DVDD to DGND REFIN/REFOUT to REFGND ECG and Analog Inputs to AGND Digital Inputs to DGND REFIN to ADCVDD AGND to DGND REFGND to AGND ECG Input Continuous Current Storage Temperature Range Operating Junction Temperature Range Reflow Profile Junction Temperature ESD HBM FICDM Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +2.5 V −0.3 V to +2.5 V −0.3 V to +2.
PAGE 14
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet AVDD CM_IN RLD_OUT RLD_SJ CM_OUT/WCT AVDD AGND AGND ADCVDD XTAL1 XTAL2 CLK_IO DVDD DGND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 NC AGND 1 ECG5_V2 2 ECG4_V1 3 ECG3_RA 4 ECG2_LL 5 ECG1_LA 6 REFIN 7 REFOUT 8 REFGND 9 EXT_RESP_LA 10 EXT_RESP_LL 11 EXT_RESP_RA 12 RESPDAC_RA 13 AGND 14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 47 DGND RESPDAC_RA 3 46 IOVDD EXT_RESP_RA 4 45 SDO EXT_RESP_LL 5 44 SCLK EXT_RESP_LA 6 43 SDI NC 1 PIN 1 2 7 AD
PAGE 15
AVDD CM_IN NC RLD_SJ NC AVDD AGND AGND ADCVDD NC NC CLK_IN DVDD DGND NC DGND DVDD SYNC_GANG PD RESET ADCVDD AGND AGND AVDD VREG_EN NC CAL_DAC_IN ADAS1000/ADAS1000-1/ADAS1000-2 NC AVDD NC Data Sheet 56 55 54 53 52 51 50 49 48 47 46 45 44 43 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 NC PIN 1 2 NC 3 NC 4 45 SDO NC 5 44 SCLK 47 DGND AGND 1 ECG5 2 ECG4 3 ECG3 4 ECG2 5 ECG1 6 REFIN 7 REFOUT 8 REFGND 9 NC 10 NC 11 NC 12 NC 13 AGND 14 46 IOVDD 43 SDI NC 6 REFGND 7 ADAS
PAGE 16
ADAS1000/ADAS1000-1/ADAS1000-2 ADAS1000 LQFP LFCSP 14 2 ADAS1000-1 LFCSP 2 ADAS1000-2 LQFP LFCSP 10 11 12 13 14 6 5 4 3 2 Data Sheet Mnemonic ECG5_V2 ECG1 ECG2 ECG3 ECG4 ECG5 EXT_RESP_RA EXT_RESP_LL EXT_RESP_LA RESPDAC_LL Description Analog Input, Chest Electrode 2 or Auxiliary Biopotential Input (V2). Analog Input 1. Analog Input 2. Analog Input 3. Analog Input 4. Analog Input 5. Optional External Respiration Input. Optional External Respiration Input. Optional External Respiration Input.
PAGE 17
Data Sheet ADAS1000 LQFP LFCSP 1, 16, 17, 32, 33, 48, 49, 64 ADAS1000/ADAS1000-1/ADAS1000-2 ADAS1000-1 LFCSP 10, 11, 12, 13, 16 ADAS1000-2 LQFP LFCSP 10, 11, 1, 3, 4, 12, 13, 5, 6, 16, 18, 16, 17, 46, 47, 20, 22, 52, 54 27, 28, 32, 33, 48, 49, 60, 62, 64 36 40 37 39 38 38 39 37 57 Description No connect. Do not connect to these pins. (see Figure 7, Figure 9, Figure 10, Figure 11). General-Purpose I/O. General-Purpose I/O. General-Purpose I/O. General-Purpose I/O. Output of Shield Driver.
PAGE 18
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 8 15 10 INPUT REFERRED NOISE (µV) 4 2 0 –2 1 2 3 4 5 6 7 8 9 10 –5 Figure 12. Input Referred Noise for 0.5 Hz to 40 Hz Bandwidth, 2 kHz Data Rate, GAIN 0 (1.4) 8 –15 09660-039 0 TIME (Seconds) 0.5Hz TO 150Hz GAIN SETTING 3 = 4.2 DATA RATE = 2kHz 10 SECONDS OF DATA 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) Figure 15. Input Referred Noise for 0.5 Hz to 150 Hz Bandwidth, 2 kHz Data Rate, GAIN 3 (4.
PAGE 19
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 0.121 0.215 AVDD = 3.3V AVDD = 3.3V 0.210 0.101 THRESHOLD (V) GAIN ERROR (%) 0.205 0.081 0.061 0.041 0.200 0.195 0.190 0.021 GAIN 0 GAIN 1 GAIN 2 GAIN 3 0.180 –40 ECG DC LEAD-OFF THRESHOLD RLD DC LEAD-OFF THRESHOLD –20 0 GAIN SETTING 2.420 0 = 1.4 1 = 2.1 2 = 2.8 3 = 4.2 HIGH THRESHOLD (V) –0.15 –0.20 2.405 2.400 2.395 2.390 2.385 GAIN ERROR G0 GAIN ERROR G1 GAIN ERROR G2 GAIN ERROR G3 –0.35 –40 –20 0 20 40 60 2.
PAGE 20
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet 0 0 AVDD = 3.3V –1 –1 –2 –2 –4 GAIN (dB) GAIN (dB) –3 –5 –6 –3 –4 –7 –8 –5 –9 10 100 1k FREQUENCY (Hz) AVDD = 3.3V –6 1 0 0 –1 –2 –2 10k 100k AVDD = 3.3V –3 –4 GAIN (dB) –5 –6 –4 –5 –6 –7 –7 –8 10 100 1k FREQUENCY (Hz) Figure 25. Filter Response with 250 Hz Filter Enabled, 2 kHz Data Rate; See Figure 72 for Digital Filter Overview 0 –9 09660-052 1 1 10 100 1k 10k 100k FREQUENCY (Hz) 09660-055 –8 –9 Figure 28.
PAGE 21
Data Sheet 805 AVDD = 3.3V AVDD = 3.3V 800 AVDD SUPPLY CURRENT (µA) 1.3005 1.2995 1.2990 1.2985 1.2980 785 780 775 0 20 40 60 80 TEMPERATURE (°C) 765 –40 0 20 40 60 80 TEMPERATURE (°C) Figure 33. Typical AVDD Supply Current vs. Temperature in Standby Mode Figure 30. VCM_REF vs. Temperature 12.65 AVDD = 3.3V 5 ECG CHANNELS ENABLED INTERNAL LDO UTILIZED 12.45 HIGH PERFORMANCE/LOW NOISE MODE 12.60 12.40 12.55 CURRENT (mA) 12.50 12.35 12.30 LOW NOISE/HIGH PERFORMANCE MODE 12.
PAGE 22
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet 0.517390 AVDD = 3.3V ECG PATH/DEFIB/CABLE IMPEDANCE = 0Ω PATIENT IMPEDANCE = 1kΩ 0.121140 RESPIRATION RATE = 10RESPPM RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 0.121135 0.121130 0.121125 0.517375 0.517370 0.121120 0.517365 0.121115 0.517360 0 5 10 15 20 25 30 TIME (Seconds) Figure 36. Respiration with 100 mΩ Impedance Variation, Using Internal Respiration Paths and Measured with a 0 Ω Patient Cable 0.663160 0.663155 0.159770 0.663150 0.
PAGE 23
Data Sheet 50 ADAS1000/ADAS1000-1/ADAS1000-2 40 30 LA LL RA V1 V2 AVDD = 3.3V 100 20 50 10 INL (µV/RTI) DNL ERROR (µV RTI) 150 LA LL RA V1 V2 AVDD = 3.3V 0 –10 0 –50 –20 –30 –100 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 INPUT VOLTAGE (V) Figure 42. DNL vs. Input Voltage Range Across Electrodes at 25°C 50 30 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 INPUT VOLTAGE (V) Figure 45. INL vs.
PAGE 24
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet 0 120 AVDD = 3.3V GAIN 0 DATA RATE = 2kHz FILTER SETTING = 150Hz –20 80 60 LOOP GAIN (dB) –60 –80 –100 –120 40 20 0 –140 –40 –160 –60 –180 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (Hz) 1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 51. Open-Loop Gain Response of ADAS1000 Right Leg Drive Amplifier Without Loading Figure 48.
PAGE 25
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 APPLICATIONS INFORMATION OVERVIEW The ADAS1000/ADAS1000-1/ADAS1000-2 are electro cardiac (ECG) front-end solutions targeted at a variety of medical applications. In addition to ECG measurements, the ADAS1000 version also measures thoracic impedance (respiration) and detects pacing artifacts, providing all the measured information to the host controller in the form of a data frame supplying either lead/vector or electrode data at programmable data rates.
PAGE 26
ADAS1000/ADAS1000-1/ADAS1000-2 CAL_DAC_IO RLD_SJ VREF CALIBRATION DAC CM_IN CM_OUT/WCT SHIELD SHIELD DRIVE AMP AVDD IOVDD ADCVDD, DVDD 1.8V REGULATORS VCM_REF (1.
PAGE 27
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 REFIN REFOUT CAL_DAC_IN RLD_SJ AVDD CM_IN VREF 10kΩ COMMONMODE AMP 10kΩ AC LEAD-OFF DAC ADCVDD, DVDD 1.8V REGULATORS IOVDD ADCVDD DVDD ADAS1000-2 VREF AC LEAD-OFF DETECTION ECG PATH ECG1 AMP ADC CS ECG2 AMP SCLK ADC SDI ECG3 DC LEADOFF/MUXES AMP ADC FILTERS, CONTROL, AND INTERFACE LOGIC SDO DRDY PD AMP ADC RESET SYNC_GANG AMP ADC GPIO0 GPIO1 ECG4 ECG5 REFGND AGND 09660-013 GPIO2 GPIO3 DGND Figure 55.
PAGE 28
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet ECG INPUTS—ELECTRODES/LEADS The ADAS1000/ADAS1000-1/ADAS1000-2 ECG product consists of 5 ECG inputs and a reference drive, RLD (right leg drive). In a typical 5-lead/vector application, four of the ECG inputs (ECG3_RA, ECG1_LA, ECG2_LL, ECG4_V1) would be used in addition to the RLD path. This leaves one spare ECG path (which could be used for other purposes, such as calibration or temperature measurement).
PAGE 29
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 The ADAS1000/ADAS1000-1/ADAS1000-2 implementation uses a dc-coupled approach, which requires that the front end be biased to operate within the limited dynamic range imposed by the relatively low supply voltage. The right leg drive loop performs this function by forcing the electrical average of all selected electrodes to the internal 1.3 V level, VCM_REF, maximizing each channel’s available signal range.
PAGE 30
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Digital Lead Configuration and Calculation ELECTRODE/LEAD FORMATION AND INPUT STAGE CONFIGURATION When the ADAS1000/ADAS1000-1/ADAS1000-2 are configured for digital lead mode (see the FRMCTL register, 0x0A[4], Table 35), the digital core will calculate each lead from the electrode signals. This is straightforward for Lead I/ Lead II/Lead III. Calculating V1’ and V2’ requires WCT, which is also computed internally for this purpose.
PAGE 31
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 CM_OUT/WCT VCM = WCT = (LA + LL + RA)/3 COMMONMODE AMP ECGCTL 0x01[10] CHCONFIG = 1 FRMCTL 0x0A[4] DATAFMT = 0 DIFFERENTIAL INPUT – LEAD FORMAT LEAD I + (LA – RA) ADC AMP ECG1_LA – LEAD III (LL – LA) + AMP ECG2_LL ADC – LEAD II (LL – RA)* + AMP ECG3_RA ADC – *GETS MULITPLED BY –1 IN DIGITAL + AMP ECG4_V1 ADC V1’ = V1 – WCT – WCT = (LA + LL + RA)/3 + AMP ECG5_V2 ADC V2’ = V2 – WCT – WCT = (LA + LL + RA)/3 09660-015 CM_IN for example RA
PAGE 32
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet VCM = RA CM_OUT/WCT COMMONMODE AMP ECG1_LA ECGCTL 0x01[10] CHCONFIG = 0 FRMCTL 0x0A[4] DATAFMT = 1 CMREFCTL 0x05[8] CEREFEN = 1 SINGLE ENDED ELECTRODE FORMAT + AMP ADC + AMP ADC + AMP ADC + AMP ADC + AMP ADC LA – RA – ECG2_LL – ECG3_RA = V3 – ECG4_V1 LL – RA V3 – RA V1 – RA – – CM_IN = RA COMMON ELECTRODE CE IN V2 – RA FRMCTL 0x0A[4] = 0 CONFIGURES SINGLE-ENDED ELECTRODE FORMAT WHERE LEADS ARE CALCULATED DIGITALLY AFTER ADC PROCESSING.
PAGE 33
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 DEFIBRILLATOR PROTECTION ESIS FILTERING The ADAS1000/ADAS1000-1/ADAS1000-2 do not include defibrillation protection on chip. Any defibrillation protection required by the application requires external components. Figure 61 and Figure 62 show examples of external defibrillator protection, which is required on each ECG channel, in the RLD path and in the CM_IN path if using the CE input mode.
PAGE 34
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet common-mode block. If the physical connection to each electrode is buffered, these buffers are omitted for clarity. COMMON-MODE SELECTION AND AVERAGING The common-mode signal can be derived from any combination of one or more electrode channel inputs, the fixed internal common-mode voltage reference, VCM_REF, or an external source connected to the CM_IN pin.
PAGE 35
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 In some cases, adding lead compensation will prove necessary, while in others lag compensation may be more appropriate. The RLD amplifier’s summing junction is brought out to a package pin (RLD_SJ) to facilitate compensation. WILSON CENTRAL TERMINAL (WCT) The flexibility of the common-mode selection averaging allows the user to achieve a Wilson central terminal voltage from the ECG1_LA, ECG2_LL, ECG3_RA electrodes.
PAGE 36
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet either case, all active channels use the same detection thresholds. CALIBRATION DAC Within the ADAS1000/ADAS1000-1, there are a number of calibration features. The 10-bit calibration DAC can be used to correct channel gain errors (to ensure channel matching) or to provide several test tones. The options are as follows: • • • DC voltage output (range: 0.3 V to 2.7 V). The DAC transfer function for dc voltage output is  code   0.3 V +  2.
PAGE 37
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Only one lead measurement can be made at one time. The respiration measurement path is not suited for use as additional ECG measurements because the internal configuration and demodulation do not align with an ECG measurement; however, the EXT_RESP_LA, EXT_RESP_RA, or EXT_RESP_LL paths can be multiplexed into one of the ECG ADC paths, if required, as discussed in the Extend Switch On Respiration Paths section.
PAGE 38
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet External Respiration Path External Respiration Capacitors The EXT_RESP_xx pins are provided for use either with the ECG electrode cables or, alternatively, with a dedicated external sensor independent of the ECG electrode path. Additionally, the EXT_RESP_xx pins are provided such that the user can measure the respiration signal at the patient side of the RFI/ ESIS protection filters.
PAGE 39
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 1nF TO 10nF RESPDAC_LA 50kHz TO 56kHz 1kΩ 100Ω RESPIRATION DAC DRIVE + ve CABLE AND ELECTRODE IMPEDANCE < 1kΩ RESPIRATION MEASURE LA CABLE EXT_RESP_LA IN-AMP AND ANTI-ALIASING 10kΩ RA CABLE ADAS1000 ±1V OVERSAMPLED HPF SAR ADC GAIN 10kΩ LPF MAGNITUDE AND PHASE EXT_RESP_RA 1/2 OF AD8606 10kΩ 0.9V 1nF TO 10nF RESPDAC_RA 1kΩ 100Ω 46.5kHz TO 64kHz ±1V 09660-025 REFOUT = 1.8V 10kΩ RESPIRATION DAC DRIVE – ve 1/2 OF AD8606 Figure 68.
PAGE 40
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet PACING ARTIFACT DETECTION FUNCTION (ADAS1000 ONLY) The pacing artifact validation function qualifies potential pacing artifacts and measures the width and amplitude of valid pulses. These parameters are stored in and available from any of the pace dataregisters (Address 0x1A, Address 0x3A to Address 0x3C). This function runs in parallel with the ECG channels.
PAGE 41
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 START ENABLE PACE DETECTION SELECT LEADS START PACE DETECTION ALGORITHM START PULSE WIDTH TIMER LOOK FOR TRAILING EDGE START NOISE FILTERS (if enabled) TRAILING EDGE DETECTED? NO YES NOISE FILTER PASSED? NO YES 2ms > PULSE WIDTH > 100µs NO YES 09660-026 FLAG PACE DETECTED UPDATE REGISTERS WITH WIDTH AND HEIGHT Figure 70.
PAGE 42
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Pace Amplitude Threshold Pace Validation Filter 2 This register (Address 0x07, see Table 32) can be used to set the minimum valid pace pulse amplitude: This filter is also used to reject sub threshold pulses such as MV pulses and inductive implantable telemetry systems. It is normally enabled and is controlled via the PACECTL register, Bit 10 (see Table 29). Filter 2 applies to all leads enabled for pace detection.
PAGE 43
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 delays are summarized in Table 14 and must be taken into account to enable correct positioning of the pace event relative to the ECG data. While these experiments validate the pace algorithm over a confined set of circumstances and conditions, they do not replace end system verification of the pacer algorithm. This can be performed in only the end system, using the system manufacturer’s specified cables and validation data set.
PAGE 44
ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 14. Relationship of ECG Waveform to Pace Indication 1, 2, 3 Data Rate 2 kHz 16 kHz 128 kHz Conditions 450 Hz ECG bandwidth 250 Hz ECG bandwidth 150 Hz ECG bandwidth 40 Hz ECG bandwidth Apparent Delay of ECG Data Relative to Pace Event 4 0.984 ms 1.915 ms 2.695 ms 7.641 ms 109 μs 0 ECG waveform delay is the time required to reach 50% of final value following a step input. Guaranteed by design, not subject to production test.
PAGE 45
Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 The ADAS1000/ADAS1000-1/ADAS1000-2 have a high performance, low noise, on-chip 1.8 V reference for use in the ADC and DAC circuits. The REFOUT of one device is intended to drive the REFIN of the same device. The internal reference is not intended to drive significant external current; for optimum performance in gang operation with multiple devices, each device should use its own internal reference. An external 1.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Right Leg Drive The ADAS1000/ADAS1000-1 have a dedicated CM_OUT pin serving as an output and a CM_IN pin as an input. In gang mode, the master device determines the common-mode voltage based on the selected input electrodes. This commonmode signal (on CM_OUT) can then be used by subsequent slave devices (applied to CM_IN) as the common-mode reference. All electrodes within the slave device are then measured with respect to the CM_IN signal from the master device.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 15.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet SERIAL INTERFACES The ADAS1000/ADAS1000-1 also provide an optional secondary serial interface that is capable of providing ECG data at the 128 kHz data rate for users wishing to apply their own digital pace detection algorithm. This is a master interface that operates with an SCLK of 20.48 MHz. STANDARD SERIAL INTERFACE The standard serial interface is LVTTL-compatible when operating from a 2.3 V to 3.6 V IOVDD supply.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Read Mode In the 128 kHz data rate, all write words are still 32-bit writes but the read words in the data packet are now 16 bits (upper 16 bits of register). There are no address bits, only data bits. Register space that is larger than 16 bits spans across 2 × 16-bit words (for example, pace and respiration).
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Internal operations are synchronized to the internal master clock at either 2.048 MHz or 1.024 MHz (ECGCTL[3]: HP = 1 and HP = 0, respectively, see Table 26). Because there is no guaranteed relationship between the internal clock and the SPI's SCLK signal, an internal handshaking scheme is used to ensure safe data transfer between the two clock domains.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 CRC Word ADAS1000 Framed data integrity is provided by CRCs. For the 128 kHz frame rates, the 16-bit CRC-CCITT polynomial is used. For the 2 kHz and 16 kHz frame rates, the 24-bit CRC polynomial used. XTAL1 CLK_IO 09660-034 In both cases, the CRC residue is preset to all 1s and inverted before being transmitted. The CRC parameters are summarized in Table 22.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet SECONDARY SERIAL INTERFACE This second serial interface is an optional interface that can be used for the user’s own pace detection purposes. This interface contains ECG data at 128 kHz data rate only. If using this interface, the ECG data is still available on the standard interface discussed previously at lower rates with all the decimation and filtering applied. If this interface is inactive, it draws no power. Data is available in 16-bit words, MSB first.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 SPI OUTPUT FRAME STRUCTURE (ECG AND STATUS DATA) Three data rates are offered for reading ECG data: low speed 2 kHz/16 kHz rates for electrode/lead data (32-bit words) and a high speed 128 kHz for electrode/lead data (16-bit words).
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet SPI REGISTER DEFINITIONS AND MEMORY MAP In 2 kHz and 16 kHz data rates, data takes the form of 32-bit words. Bit A6 to Bit A0 serve as word identifiers. Each 32-bit word has 24 bits of data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data). Table 24.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 CONTROL REGISTERS DETAILS For each register address, the default setting is noted in a default column in addition to being noted in the function column by “(default)”; this format applies throughout the register map. Table 25. Serial Bit Assignment B31 R/W [B30:B24] Address bits [B23:B0] Data bits (MSB first) Table 26.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 27. Lead-Off Control Register (LOFFCTL) Address 0x02, Reset Value = 0x000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 00 Bit 23 22 21 20 19 18 17 16 15 14 13 12 [11:9] [8:7] Name LAPH LLPH RAPH V1PH V2PH CEPH LAACLOEN LLACLOEN RAACLOEN V1ACLOEN V2ACLOEN CEACLOEN Reserved ACCURRENT R/W 00 000 [6:5] [4:2] Reserved DCCURRENT R/W 0 1 ACSEL R/W 0 0 LOFFEN Function AC lead-off phase.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 28. Respiration Control Register (RESPCTL) Address 0x03, Reset Value = 0x000000 1 R/W Default R/W 0 Bit [23:17] 16 Name Reserved RESPALTFREQ R/W 0 15 RESPEXTSYNC R/W 0 14 RESPEXTAMP R/W 0 13 RESPOUT R/W 0 12 RESPCAP R/W 0000 [11:8] RESPGAIN [3:0] R/W 0 7 RESPEXTSEL R/W 00 [6:5] RESPSEL [1:0] R/W 00 [4:3] RESPAMP R/W 00 [2:1] RESPFREQ R/W 0 0 RESPEN 1 Function Reserved, set to 0.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 29.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 30.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 31.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 32. Pace Amplitude Threshold Register (PACEAMPTH) Address 0x07, Reset Value = 0x242424 1 R/W R/W R/W R/W 1 Default 0010 0100 0010 0100 0010 0100 Bit [23:16] [15:8] [7:0] Name PACE3AMPTH PACE2AMPTH PACE1AMPTH Function Pace amplitude threshold Threshold = N × 2 × VREF/GAIN/216 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 33.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 34. Calibration DAC Register (CALDAC) Address 0x09, Reset Value = 0x002000 1 R/W R/W Default 0 1 Bit [23:14] 13 Name Reserved CALCHPEN R/W 0 12 CALMODEEN R/W 0 11 CALINT R/W 0 10 CALDACEN R/W 0000000000 [9:0] CALDATA[9:0] 1 Function Reserved, set to 0. Calibration chop clock enable. The calibration DAC output (CAL_DAC_IO) can be chopped to lower 1/f noise. Chopping is performed at 256 kHz. 0 = disabled. 1 (default) = enabled.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 35.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 36.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 39. Pace Edge Threshold Register (PACEEDGETH) Address 0x0E, Reset Value = 0x000000 1 R/W R/W R/W Default 0 0 Bit [23:16] [15:8] Name PACE3EDGTH PACE2EDGTH R/W 0 [7:0] PACE1EDGTH 1 Function Pace edge trigger threshold 0 = PACEAMPTH/2 1 = VREF/GAIN/216 N = N × VREF/GAIN/216 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 40.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 42. Read Pace Detection Data/Status Register (PACEDATA) Address 0x1A, Reset Value = 0x000000 1, 2, 3 R/W R Default 0 Bit 23 Name Pace 3 detected R 000 [22:20] Pace Channel 3 width R 0000 [19:16] Pace Channel 3 height R 0 15 Pace 2 detected R 000 [14:12] Pace Channel 2 width R 0000 [11:8] Pace Channel 2 height R 0 7 Pace 1 detected R 000 [6:4] Pace Channel 1 width R 0000 [3:0] Pace Channel 1 height Function Pace 3 detected.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 45. Lead-Off Status Register (LOFF) Address 0x1D, Reset Value = 0x000000 R/W R Default 0 R R 0 0 R 0 Bit 23 22 21 20 19 18 13 Name RLD lead-off Status LA lead-off status LL lead-off status RA lead-off status V1 lead-off status V2 lead-off status CELO [17:14] 12 11 10 9 8 [7:0] Reserved LAADCOR LLADCOR RAADCOR V1ADCOR V2ADCOR Reserved Function Electrode connection status.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 47. Operating State Register (OPSTAT) Address 0x1F, Reset Value = 0x000000 1 R/W R R R Default 0 0 0 Bit [23:4] 3 2 Name Reserved Internal error Configuration status R 0 1 PLL lock R 0 0 PLL locked status 1 Function Reserved. Internal digital failure. This is set if an error is detected in the digital core. This bit is set after a reset indicating that the configuration has not been read yet. Once the configuration is set, this bit is ready.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 49. User Gain Calibration Registers (CALxx) Address 0x21 to Address 0x25, Reset Value = 0x000000 R/W Default Bit Name Function [31:24] Address [7:0] 0x21: calibration LA. 0x22: calibration LL. 0x23: calibration RA. 0x24: calibration V1. 0x25: calibration V2. User can choose between default calibration values or user calibration values for GAIN 0, GAIN 1, GAIN 2. Note that for GAIN 3, there is no factory calibration.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 51.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 52. Frame Header (FRAMES) Address 0x40, Reset Value = 0x800000 1 R/W R R Default 1 0 Bit 31 30 Name Marker Ready bit R 0 [29:28] Overflow [1:0] R 0 27 Fault R 0 26 Pace 3 detected R 0 25 Pace 2 detected R 0 24 Pace 1 detected R 0 23 Respiration R 0 22 Lead-off detected R 0 21 DC lead-off detected R 0 20 ADC out of range 0 [19:0] Reserved 1 Function Header marker, set to 1 for the header.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet EXAMPLES OF INTERFACING TO THE ADAS1000 The following examples shows register commands required to configure the ADAS1000 device into particular modes of operation and to start framing ECG data. Example 2: Enable Respiration and Stream Conversion Data 1. Example 1: Initialize the ADAS1000 for ECG Capture and Start Streaming Data 1. 2. 3. 4. 5. Write 1 configures the CMREFCTL register for CM = WCT = (LA + LL + RA)/3; RLD is enabled onto the RLD_OUT electrode.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Example 5: Enable Pace Detection and Stream Conversion Data 1. 1. 2. 3. 4. 5. 6. 7. Write 1 configures the CMREFCTL register to VCM_REF = 1.3 V (no electrodes contribute to VCM). RLD is enabled to RLD_OUT, and the shield amplifier enabled. Write 2 addresses the TESTTONE register to enable the 150 Hz sine wave onto all electrode channels.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Example 6: Writing to Master and Slave Devices and Streaming Conversion Data Master Configuration Slave Configuration 1. Write 4 configures the FRMCTL register to output nine 1. Write 1 configures the FRMCTL register to output seven words per frame/packet (note that this differs from the words per frame/packet. The frame/packet of words consist number of words in a frame available from the slave of the header, five ECG words, and lead-off. The frame is device).
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 SOFTWARE FLOWCHART Figure 81 shows a suggested sequence of steps to be taken to interface to multiple ADAS1000/ADAS1000-1/ADAS1000-2 devices. POWER UP ADAS1000 DEVICES WAIT FOR POR ROUTINE TO COMPLETE, 1.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY The ADAS1000/ADAS1000-1/ADAS1000-2 should have ample supply decoupling of 0.01 μF on each supply pin located as close to the device pin as possible, ideally right up against the device. In addition, there should be one 4.7 μF capacitor for each of the power domains, AVDD and IOVDD, again located as close to the device as possible. IOVDD is best split from AVDD due to its noisy nature.
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 0.42 0.24 0.60 0.42 0.24 0.275 43 PIN 1 INDICATOR 8.75 BSC SQ 6.05 5.95 SQ 5.85 *EXPOSED PAD 1 0.50 BSC 0.75 0.65 0.55 29 14 15 28 TOP VIEW BOTTOM VIEW 6.50 REF 0.70 MAX 0.65 NOM 12° MAX 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF 06-20-2012-A SEATING PLANE *FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 82.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet ORDERING GUIDE Model 1 ADAS1000BSTZ ADAS1000BSTZ-RL ADAS1000BCPZ ADAS1000BCPZ-RL ADAS1000-1BCPZ ADAS1000-1BCPZ-RL ADAS1000-2BSTZ ADAS1000-2BSTZ-RL ADAS1000-2BCPZ ADAS1000-2BCPZ-RL EVAL-ADAS1000SDZ EVAL-SDP-CB1Z Description 5 ECG Channels, Pace Algorithm, Respiration Circuit 5 ECG Channels, Pace Algorithm, Respiration Circuit 5 ECG Channels, Pace Algorithm, Respiration Circuit 5 ECG Channels, Pace Algorithm, Respiration Circuit 5 ECG Channels 5 ECG Channels Compan
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Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 NOTES Rev.
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ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09660-0-1/13(A) Rev.