Datasheet

ADAS1000-3/ADAS1000-4 Data Sheet
Rev. A | Page 60 of 76
Table 35. Calibration DAC Register (CALDAC) Address 0x09, Reset Value = 0x002000
1
R
/W
Default Bit Name Function
0 [23:14] Reserved Reserved, set to 0.
R/W 1 13 CALCHPEN
Calibration chop clock enable. The calibration DAC output (CAL_DAC_IO) can be
chopped to lower 1/f noise. Chopping is performed at 256 kHz.
0 = disabled.
1 (default) = enabled.
R/W 0 12 CALMODEEN Calibration mode enable.
0 (default)
= disable calibration mode.
1 = enable calibration mode; connect CAL DAC_IO, begin data acquisition on ECG
channels.
R/W 0 11 CALINT Calibration internal or external.
0 (default) = external calibration to be performed externally by looping CAL_DAC_IO
around into ECG channels.
1 = internal calibration; disconnects external switches for all ECG channels and
connects calibration DAC signal internally to all ECG channels.
R/W 0 10 CALDACEN Enable 10-bit calibration DAC for calibration mode or external use.
0 (default)
= disable calibration DAC.
1 = enable calibration DAC. If a master device and not in calibration mode, also
connects the calibration DAC signal out to the CAL_DAC_IO pin for external use. If in
slave mode, the calibration DAC is disabled to allow master to drive the slave
CAL_DAC_IO pin. When the calibration DAC is enabled, ac lead-off is disabled.
R/W 0000000000 [9:0] CALDATA[9:0] Set the calibration DAC value.
1
To ensure successful update of the calibration DAC, the serial interface must issue four additional SCLK cycles after writing the new calibration DAC register word.