Datasheet

ADAS1000-3/ADAS1000-4 Data Sheet
Rev. A | Page 52 of 76
SPI REGISTER DEFINITIONS AND MEMORY MAP
In 2 kHz and 16 kHz data rates, data takes the form of 32-bit words. Bit A6 to Bit A0 serve as word identifiers. Each 32-bit word has
24 bits of data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data).
Table 25. SPI Register Memory Map
R
/W
1
A[6:0] D[23:0] Register Name Table Register Description Reset Value
R 0x00 XXXXXX NOP NOP (no operation) 0x000000
R/W 0x01 dddddd ECGCTL
Table 27
ECG control 0x000000
R/W 0x02 dddddd LOFFCTL
Table 28
Lead-off control 0x000000
R/W 0x03 dddddd RESPCTL
Table 29
Respiration control
2
0x000000
R/W 0x04 dddddd PACECTL
Table 30
Pace detection control 0x000F88
R/W 0x05 dddddd CMREFCTL
Table 31
Common-mode, reference, and shield drive control 0xE00000
R/W 0x06 dddddd GPIOCTL
Table 32
GPIO control 0x000000
R/W 0x07 dddddd PACEAMPTH
Table 33 Pace amplitude threshold
2
0x242424
R/W 0x08 dddddd TESTTONE
Table 34
Test tone 0x000000
R/W 0x09 dddddd CALDAC
Table 35
Calibration DAC 0x002000
R/W 0x0A dddddd FRMCTL
Table 36
Frame control 0x079000
R/W 0x0B dddddd FILTCTL
Table 37
Filter control 0x000000
R/W 0x0C dddddd LOFFUTH
Table 38
AC lead-off upper threshold 0x00FFFF
R/W 0x0D dddddd LOFFLTH
Table 39
AC lead-off lower threshold 0x000000
R/W 0x0E dddddd PACEEDGETH
Table 40 Pace edge threshold
2
0x000000
R/W 0x0F dddddd PACELVLTH
Table 41 Pace level threshold
2
0x000000
R 0x11 XXXXXX LADATA
Table 42
LA or Lead I data 0x000000
R 0x12 XXXXXX LLDATA
Table 42
LL or Lead II data 0x000000
R 0x13 XXXXXX RADATA
Table 42
RA or Lead III data 0x000000
R 0x1A XXXXXX PACEDATA
Table 43 Read pace detection data/status
2
0x000000
R 0x1B XXXXXX RESPMAG
Table 44 Read respiration data—magnitude
2
0x000000
R 0x1C XXXXXX RESPPH
Table 45
Read respiration data—phase
2
0x000000
R 0x1D XXXXXX LOFF
Table 46
Lead-off status 0x000000
R 0x1E XXXXXX DCLEAD-OFF
Table 47
DC lead-off 0x000000
R 0x1F XXXXXX OPSTAT
Table 48
Operating state 0x000000
R/W 0x21 dddddd CALLA
Table 49
User gain calibration LA 0x000000
R/W 0x22 dddddd CALLL
Table 49
User gain calibration LL 0x000000
R/W 0x23 dddddd CALRA
Table 49
User gain calibration RA 0x000000
R 0x31 dddddd LOAMLA
Table 50
Lead-off amplitude for LA 0x000000
R 0x32 dddddd LOAMLL
Table 50
Lead-off amplitude for LL 0x000000
R 0x33 dddddd LOAMRA
Table 50
Lead-off amplitude for RA 0x000000
R 0x3A dddddd PACE1DATA
Table 51 Pace1 width and amplitude
2
0x000000
R 0x3B dddddd PACE2DATA
Table 51 Pace2 width and amplitude
2
0x000000
R 0x3C dddddd PACE3DATA
Table 51 Pace3 width and amplitude
2
0x000000
R 0x40 dddddd FRAMES
Table 52
Frame header 0x800000
R 0x41 XXXXXX CRC
Table 53
Frame CRC 0xFFFFFF
x Other XXXXXX Reserved
3
Reserved XXXXXX
1
R/W = register both readable and writable; R = read only.
2
ADAS1000-4 model only, ADAS1000-3 model does not contain these features.
3
Reserved bits in any register are undefined. In some cases, a physical (but unused) memory bit may be present—in other cases not. Do not issue commands to
reserved registers/space. Read operations of unassigned bits are undefined.