Datasheet

ADAS1000-3/ADAS1000-4 Data Sheet
Rev. A | Page 50 of 76
SECONDARY SERIAL INTERFACE
This second serial interface is an optional interface that
can be used for the user’s own pace detection purposes.
This interface contains ECG data at 128 kHz data rate only.
If using this interface, the ECG data is still available on the
standard interface discussed previously at lower rates with all
the decimation and filtering applied. If this interface is inactive,
it draws no power.
Data is available in 16-bit words, MSB first.
This interface is a master interface, with the ADAS1000-3/
ADAS1000-4 providing the SCLK,
CS
, SDO. Is it shared
across some of the existing GPIO pins as follows:
• GPIO1/MSCLK
• GPIO0/
MCS
• GPIO2/MSDO
This interface can be enabled via the GPIO register (see
Table 32).
Figure 74. Master SPI Interface for External Pace Detection Purposes
The data format of the frame starts with a header word, three
ECG data-words, two words filled with zeros and completes
with the same CRC word as documented in Table 23 for the
128 kHz rate. All words are 16 bits. MSCLK runs at approxi-
mately 20 MHz and the
MCS
function is asserted for the entire
frame with the data available on MSDO on the falling edge of
MSCLK. MSCLK idles high when
MCS
is deasserted.
Table 24. Master SPI Frame Format; All Words are 16 Bits
Word
1 2 3 4 5 6
Header
Lead I/LA Lead II/LL Lead III/RA All 0’s All 0’s CRC
The header word consists of four bits of all 1s followed by a 12-
bit sequence counter. This sequence counter increments after
every frame is sent, thereby allowing the user to tell if any
frames have been missed and how many.
RESET
There are two methods of resetting the ADAS1000-3/ADAS1000-4
to power-on default. Bringing the
RESET
line low or setting
the SWRST bit in the ECGCTL register (Table 27) resets the
contents of all internal registers to their power-on reset state.
The falling edge of the
RESET
pin initiates the reset
process;
DRDY
goes high for the duration, returning low when
the
RESET
process is complete. This sequence takes 1.5 ms
maximum. Do not write to the serial interface while
DRDY
is
high handling a
RESET
command. When
DRDY
returns low,
normal operation resumes and the status of the
RESET
pin is
ignored until it goes low again. Software reset using the SWRST
bit (see Table 27) requires that a NOP (no operation) command
be issued to complete the reset cycle.
PD FUNCTION
The
PD
pin powers down all functions in low power mode.
The digital registers maintain their contents. The power-down
function is also available via the serial interface (ECG control
register, see Table 27).
ADAS1000-4
MASTER SPI
SCLK
CS
MCS/GPIO0
MICROCONTROLLER/
DSP
MSDO/GPIO2
MISO/GPIO
MSCLK/GPIO1
10997-035