Datasheet

ADAS1000-3/ADAS1000-4 Data Sheet
Rev. A | Page 40 of 76
While these experiments validate the pace algorithm over a
confined set of circumstances and conditions, they do not
replace end system verification of the pacer algorithm. This
can be performed in only the end system, using the system
manufacturer’s specified cables and validation data set.
EVALUATING PACE DETECTION PERFORMANCE
ECG simulators offer a convenient means of studying the
ADAS1000’s performance and ability to capture pace signals
over the range of widths and heights defined by the various
regulatory standards. While the ADAS1000-3/ADAS1000-4
pace detection algorithm is designed to conform to medical
instrument standards, some simulators put out signals wider
(or narrower) than called for in the standards, and these will
be rejected as invalid by the ADAS1000-3/ADAS1000-4’s
algorithm.
The ADAS1000-3/ADAS1000-4’s pace width acceptance
window is tightest at the 2 ms limit. If this proves problematic,
margin can be obtained by reducing the master clock frequency.
For example, using an 8.000 MHz crystal in place of the recom-
mended 8.192 MHz crystal increases the high limit of the pace
acceptance window from 2.000 ms to 2.048 ms. The low limit
also increases, but this will not impair the algorithm's ability
to detect 100 µs pace pulses.
Changing the clock frequency affects all other ADAS1000-
3/ADAS1000-4 frequency-related functions. Continuing with
the 8.000 MHz example, the −3 dB frequencies for ECG will
scale by a factor of 8000/8192, with 40 Hz becoming 39.06 Hz
and 150 Hz becoming 146.5 Hz, both still well within regulatory
requirements. The respiration and ac leads-off frequencies,
as well as the output data rates, will also scale by the same
8000/8192 fraction.
PACE LATENCY
The pace algorithm always examines 128 kHz, 16-bit ECG data,
regardless of the selected frame rate and ECG filter setting. A
pace pulse is qualified when a valid trailing edge is detected
and is flagged in the next available frame header. Pace and ECG
data is always correctly time-aligned at the 128 kHz frame rate,
but the additional filtering inherent in the slower frame rates
delays the frame's ECG data relative to the pace pulse flag.
These delays are summarized in Table 15 and must be taken
into account to enable correct positioning of the pace event
relative to the ECG data.
There is an inherent one-frame-period uncertainty in the exact
location of the pace trailing edge.
PACE DETECTION VIA SECONDARY SERIAL
INTERFACE
The ADAS1000-3/ADAS1000-4 provide a second serial
interface for users to implement their own pace detection
schemes. This interface is configured as a master interface. It
provides ECG data at the 128 kHz data rate only. The purpose
of this interface is to allow the user to access the ECG data at a
rate sufficient to allow them to run their own pace algorithm,
while maintaining all the filtering and decimation of the ECG
data that the ADAS1000-3/ADAS1000-4 offer on the standard
serial interface (2 kHz and 16 kHz data rates). This dedicated
pace interface uses three of the four GPIO pins, leaving one
GPIO pin available even when the secondary serial interface is
enabled. Note that the on-chip digital calibration to ensure
channel gain matching does not apply to data that is available
on this interface. This interface is discussed in more detail in
the Secondary Serial Interface section.
FILTERING
Figure 68 shows the ECG digital signal processing. The ADC
sample rate is programmable. In high performance mode, it
is 2.048 MHz; in low power mode, the sampling rate is reduced
to 1.024 MHz. The user can tap off framing data at one of three
data rates, 128 kHz, 16 kHz, or 2 kHz. Note that although the
data-word width is 24 bits for the 2 kHz and 16 kHz data rate,
the usable bits are 19 and 18, respectively.
The amount of decimation depends on the selected data rate,
with more decimation for the lower data rates.
Four selectable low-pass filter corners are available at the 2 kHz
data rate.
Filters are cleared by a reset. Table 15 shows the filter latencies
at the different data rates.