Datasheet

Data Sheet ADAS1000-3/ADAS1000-4
Rev. A | Page 37 of 76
Some users may not wish to use three pace leads for detection.
In this case, Lead II would be the vector of choice because this
lead is likely to display the best pacing artifact. The other two
pace instances can be disabled if not in use.
The on-chip filtering contributes some delay to the pace signal
(see the Pace Latency section).
Choice of Leads
Three identical state machines are available and can be
configured to run on up to three of four possible leads (Lead I,
Lead II, Lead III, and aVF) for pacing artifact detection. All
necessary lead calculations are performed internally and are
independent of EGG channel settings for output data rate, low-
pass filter cutoff, and mode (electrode, analog lead, common
electrode). These calculations take into account the available
front-end configurations as detailed in Tabl e 14.
The pace detection algorithm searches for pulses by analyzing
samples in the 128 kHz ECG data stream. The algorithm
searches for an edge, a peak, and a falling edge as defined by
values in the PACEEDGETH, PACEAMPTH, and PACELVLTH
registers, along with fixed width qualifiers. The post-reset
default register values can be overwritten via the SPI bus, and
different values can be used for each of the three pace detection
state machines.
The first step in pace detection is to search the data stream for
a valid leading edge. Once a candidate edge has been detected,
the algorithm begins searching for a second, opposite-polarity
edge that meets with pulse width criteria and passes the
(optional) noise filters. Only those pulses meeting all the
criteria are flagged as valid pace pulses. Detection of a valid
pace pulse sets the flag(s) in the frame header register and
stores amplitude and width information in the PACEDATA
register (Address 0x1A; see Table 43). The pace algorithm
looks for a negative or positive pulse.
Table 14. Pace Lead Calculation
0x01 [10]
1
0x05 [8]
2
Configuration
0x04 [8:3]
3
00 01 10 11
Lead I
(LA − RA)
Lead II
(LL − RA)
Lead III
(LL − LA)
aVF
(Lead II + Lead III)/2
0 0 Digital leads LA − RA
CH1 − CH3
LL − RA
CH2 − CH3
LL − LA
CH2 − CH1
LL − (LA + RA)/2
CH2 − (CH1 + CH3)/2
0 1
Common
electrode leads
Lead I
CH1
Lead II
CH2
Lead II
–
Lead I
CH2 − CH1
Lead II − 0.5 × Lead I
CH2 − 0.5 × CH1
1 X Analog leads Lead I
CH1
Lead II
− CH3
Lead III
CH2
Lead II − 0.5 × Lead I − CH3 − 0.5 × CH1
1
Register ECGCTL, Bit CHCONFIG, see Table 27.
2
Register CMREFCTL, Bit CEREFEN, see Table 31.
3
Register PACECTL, Bit PACExSEL [1:0], see Table 30.